Page 3 · Differential current mode

LVDS

Low-Voltage Differential Signaling: a constant current steered through a 100 Ω termination. The basis of OpenLDI display links, FPD-Link and many ADC and sensor interfaces.

StandardTIA/EIA-644 (electrical); OpenLDI / FPD-Link for displays

SignalingDifferential, current mode, DC-coupled

Levels|V_OD| 247–454 mV, V_OS 1.125–1.375 V, RX threshold ±100 mV

RateHundreds of Mb/s to ~1 Gb/s per pair; 7 × PCLK in OpenLDI

How it works

The driver is a constant current source (nominally 3.5 mA) and a bridge of four switches. The data only decides which way the current goes through the 100 Ω termination at the receiver, so the receiver sees +350 mV or −350 mV. The pair sits on a common-mode voltage of about 1.2 V, set by the driver.

V_OD = I × R_T = 3.5 mA × 100 Ω = 350 mV P ≈ 3.5 mA × VDD ≈ 12 mW per pair at 3.3 VThe supply current is constant whether the data is 1, 0 or toggling. That is the main reason LVDS is quiet: no di/dt on the rails, little ground bounce, and the opposite currents on the two wires cancel each other's magnetic field.

Computed example. A ground shift or coupled noise lands on both wires equally, so it is larger than the signal itself, but it vanishes in P − N. The receiver accepts any common mode within roughly 0 to 2.4 V.

Parameter	Value (TIA/EIA-644)
Differential output \|V_OD\|	247 – 454 mV
Offset (common-mode) voltage V_OS	1.125 – 1.375 V
Receiver threshold	±100 mV
Receiver input range	~0 – 2.4 V (so ±1 V of ground shift)
Termination	100 Ω differential at the receiver
Variants	sub-LVDS (~150 mV around 0.9 V), mini-LVDS (TCON to column drivers), SLVS-400 (~200 mV around 200 mV)

OpenLDI: video over LVDS

For displays, each pair shifts out 7 bits per pixel clock and the clock pair runs at the pixel rate. Four data pairs give 28 bits: 24 bits of RGB plus HSYNC, VSYNC and DE. At 74.25 MHz (720p60) each pair runs at 520 Mb/s, one bit every 1.9 ns. The receiver multiplies the clock by 7 with a PLL and samples each slot, so pair-to-pair skew comes out of that 1.9 ns.

A single-link 24-bit OpenLDI interface. A dual link adds a second set (odd and even pixels) for panels whose pixel clock exceeds the single link's limit, roughly 85–112 MHz depending on the parts. The VESA and JEIDA maps put the bits in different pairs; a mismatch gives wrong colors, not a blank screen.

LVDS outside displays

The same signaling carries ADC and sensor data into FPGAs: high-speed ADCs, image sensors (sub-LVDS or SLVS), and the TI AWR2243's LVDS debug and capture port, which streams raw ADC samples on up to four data lanes plus a bit clock and a frame clock. In an FPGA, LVDS pins land in a bank whose VCCO and on-die termination must be set to match.

Critical design considerations

Area	Consideration	Why (physics)	Rule of thumb
SI	Differential impedance	Reflections at any impedance change; receiver has 100 Ω termination	100 Ω ± 10% differential routing on PCB, flex and cable; no stubs; termination at the receiver only.
SI	Intra-pair skew	Skew converts differential to common mode: less signal, more radiation	Match P to N within ~0.1–0.15 mm (~1 ps); serpentine at the mismatched end.
SI	Pair-to-pair skew (OpenLDI)	Every pair is sampled against the forwarded clock within one 7×PCLK slot	Match data pairs to the clock pair; check the receiver's skew margin (RSKM) against PCB + cable skew.
SI	Crosstalk between pairs	Coupled noise is not common mode if it hits one wire more than the other	Spacing between pairs ≥ 3× the intra-pair gap; ground between pairs in flex cables.
PI	Clean PLL supply for the 7× multiplier	Supply noise on the PLL becomes jitter in the sampling clock	Separate filtered supply (ferrite + caps or LDO) for the LVDS PLL on both ends.
EMC	Cable and flex emissions	Any imbalance becomes common-mode current on the cable, which radiates efficiently	Tightly coupled pairs, a solid return in the flex, common-mode chokes only if measured to be needed; spread-spectrum clocking where the panel accepts it.
ESD	Exposed connector	Panel connectors are handled during assembly	Low-capacitance TVS (≤ 1–2 pF at these rates) at the connector, symmetric on P and N.
Other	Fail-safe and power-up	An undriven or open input can float into the threshold and chatter	Use receivers with fail-safe biasing; sequence panel VDD before LVDS outputs per the panel datasheet; never drive an unpowered panel.
Other	Bit mapping	VESA and JEIDA put different color bits on each pair	Confirm the map and 6- vs 8-bit mode; set the SoC and panel SELECT strap to match.