Page 2 · Single-ended

LVCMOS

The default digital I/O: a push-pull CMOS output that drives the wire rail to rail. Simple and universal, and limited by reflections, ground bounce and EMI once edges get fast.

StandardJEDEC JESD8 family (JESD8-7 for 1.8 V, JESD8-5 for 2.5 V, LVTTL-compatible 3.3 V)

SignalingSingle-ended, push-pull, rail to rail, DC-coupled

Rails3.3, 2.5, 1.8, 1.2 V I/O banks

Practical speed~100–150 MHz on short traces; parallel RGB rarely above ~100 MHz

How it works

An LVCMOS output is a PMOS transistor to VDDIO and an NMOS transistor to ground. One is on at a time. A 1 connects the wire to VDDIO through the PMOS on-resistance; a 0 connects it to ground. The receiver is a CMOS inverter whose switching point sits near VDDIO/2, with thresholds guaranteed as fractions of the supply.

VDDIO	V_IH min	V_IL max	V_OH min	V_OL max
3.3 V (LVTTL-compatible)	2.0 V	0.8 V	2.4 V (VDD − 0.2 V at light load)	0.4 V
2.5 V	1.7 V	0.7 V	2.0 V	0.4 V
1.8 V	0.65 × VDD (1.17 V)	0.35 × VDD (0.63 V)	VDD − 0.45 V	0.45 V
1.2 V	0.65 × VDD	0.35 × VDD	VDD − 0.3 V (typ.)	0.3 V (typ.)

The difference between V_OH and V_IH (and V_IL and V_OL) is the noise margin: at 3.3 V about 0.4 V high and 0.4 V low. Everything that disturbs the wire (ground bounce, crosstalk, reflections, supply droop) has to fit inside it.

Energy per edge

P = α · C · V² · f24 data lines toggling with α = 0.25 at 74 MHz into 15 pF each at 3.3 V: 24 × 0.25 × 15 pF × 10.9 V² × 74 MHz ≈ 73 mW, all of it as current spikes in the I/O rail and ground. The same bus at 1.8 V costs 30% of that.

Reflections and why series termination works

A CMOS driver has an output impedance of about 10–30 Ω, much lower than a 50 Ω trace, and the CMOS input at the far end is nearly an open circuit. A step launched into the trace reflects off the open end with Γ = +1 (the voltage doubles) and then off the low-impedance driver with a negative Γ, so it rings.

Computed with a lattice (bounce) model: 3.3 V step, 0.4 ns rise, 50 Ω trace with 1 ns one-way delay (about 15 cm of FR-4), high-impedance receiver. The low-impedance driver launches 2.75 V, which doubles at the open end and then rings. Matching the source to 50 Ω launches half the swing; the far-end reflection completes it exactly once.

R_series = Z₀ − R_out ≈ 50 − 15 ≈ 33 ΩThe launched wave is VDD·Z₀/(Z₀ + R_out + R_series) = VDD/2. It doubles at the open far end to exactly VDD, and the reflection is absorbed at the matched source. Only the far end sees a clean edge, so series termination suits point-to-point nets; on a multi-drop bus, middle receivers see the half-step.

Pins from processor to device

28 single-ended signals plus control. Series resistors sit next to the processor pins; data and sync are sampled on the PCLK edge chosen in the panel datasheet. A DVP camera input is the same bus in the other direction: PCLK, HSYNC, VSYNC and D[7:0] to D[11:0] driven by the sensor.

Panel timing is defined by the pixel clock and the porches. For 800×480 at 60 Hz with typical blanking (1056 × 525 total), PCLK = 1056 × 525 × 60 ≈ 33 MHz. A 1280×800 panel needs about 71 MHz. Beyond about 100 MHz, LVDS or MIPI DSI take over.

Critical design considerations

Area	Consideration	Why (physics)	Rule of thumb
SI	Reflections and ringing	Driver impedance ≪ Z₀, receiver ≈ open; Γ = +1 at the load	Series R at the driver = Z₀ − R_out, placed within a few mm of the pin. Simulate with IBIS models.
SI	Setup and hold at the receiver	Data and PCLK travel different paths; skew eats the window	Length-match data to PCLK (±5 mm is generous at 33 MHz, tighten as PCLK rises). Pick the sampling edge with the most margin.
SI	Crosstalk	Mutual capacitance and inductance between parallel traces; worst near-end with fast edges	Spacing ≥ 2–3× trace height above plane; keep PCLK away from data or guard it with ground.
SI	Edge rate	Fast edges make every trace a transmission line and raise harmonics	Use the slowest drive strength / slew setting that meets timing.
PI	Simultaneous switching output (SSO) noise	28 outputs switching together: V = L_pkg · N · di/dt on ground and VDDIO, which shifts thresholds	Decoupling at every VDDIO ball, short via to plane; limit drive strength; spread ground balls; check the SoC's SSO guidelines.
PI	I/O rail droop	C·V²·f current arrives in pulses at PCLK rate	100 nF + 1 µF per bank close to the balls; low-inductance planes.
EMC	Radiated emissions	Harmonics of PCLK on 28 unshielded lines, often over a flex to the panel	Spread-spectrum PCLK if the panel tolerates it, slow edges, solid return in the flex, ferrites only where measured.
ESD	Panel connector pins exposed in assembly	CMOS gates break down at a few volts above VDD	TVS arrays at the connector for exposed lines; series R also limits ESD current.
Other	Voltage domains and power sequencing	A 3.3 V panel input driven by a 1.8 V SoC bank fails V_IH; driving an unpowered panel back-feeds through its ESD diodes	Match VDDIO to the panel or add level shifters; keep outputs low (or tri-stated) until panel VDD is up.