Page 5 · AC-coupled SerDes and MIPI

DP, eDP and DSI

DisplayPort's packetized, AC-coupled main link and its AUX-based training, the embedded version used for internal panels, and MIPI DSI for short-reach displays.

DisplayPort: a packet SerDes for video

DisplayPort was designed as a SerDes from the start: no clock pair, AC-coupled lanes, and a separate low-speed channel (AUX) for negotiation. Video, audio and secondary data are packed into a micro-packet stream that is spread across 1, 2 or 4 lanes.

Version / rate name	Per lane	Coding	4-lane payload
RBR (DP 1.x)	1.62 Gb/s	8b/10b	5.18 Gb/s
HBR	2.7 Gb/s	8b/10b	8.64 Gb/s
HBR2 (DP 1.2)	5.4 Gb/s	8b/10b	17.28 Gb/s
HBR3 (DP 1.3/1.4)	8.1 Gb/s	8b/10b	25.92 Gb/s
UHBR10 / 13.5 / 20 (DP 2.x)	10 / 13.5 / 20 Gb/s	128b/132b	up to ~77 Gb/s

The main link from first principles

CML driver, AC-coupled. A current-mode-logic stage with 50 Ω source terminations drives each pair through 75–200 nF series capacitors. The receiver biases its own common mode, so source and sink can use different supplies and grounds.
DC balance and embedded clock. 8b/10b coding (or 128b/132b with scrambling) gives zero average and bounded run length, which the AC coupling and the receiver's clock recovery both need.
Swing and pre-emphasis as knobs. The source can raise its output and boost transition bits to make up for channel loss.

Pre-emphasis is a transmit-side high-pass filter. Transition bits carry the high-frequency content the cable will attenuate, so they are sent larger. DisplayPort defines four swing levels (about 0.4, 0.6, 0.8 and 1.2 V peak-to-peak differential) and four pre-emphasis levels (0, 3.5, 6 and 9.5 dB), chosen during link training.

Link training over AUX

Hot plug. The sink raises HPD. Later, a short HPD pulse (an IRQ) asks the source to check sink status.
Read capabilities. The source reads the sink's DPCD registers and EDID over AUX: a 1 Mb/s Manchester-coded half-duplex differential channel (Fast AUX goes higher).
Clock recovery phase. The source sends training pattern 1 at a chosen rate and lane count; the sink reports whether each lane's CDR has locked and requests swing / pre-emphasis changes.
Channel equalization phase. Training pattern 2, 3 or 4; the sink adjusts its equalizer and reports symbol lock and inter-lane alignment.
Fallback. If training fails, the source drops the rate or lane count and repeats. A marginal channel often shows up as a link that silently trains at a lower rate.

eDP: DisplayPort inside the box

Embedded DisplayPort uses the same main link and AUX for internal panels, adds panel power and backlight control to the connector, and adds power-saving features such as Panel Self Refresh, where the panel keeps showing a stored frame and the source shuts its link down.

eDP to a laptop-class panel. External DisplayPort uses the same main link and AUX, adds DP_PWR (3.3 V), CONFIG pins and ESD at a 20-pin connector, and may need a retimer. Lane count can be 1, 2 or 4 depending on resolution.

MIPI DSI

DSI (Display Serial Interface) runs over MIPI D-PHY (or C-PHY), the same PHY described in the CSI-2 primer. It has two operating styles. In video mode the host streams pixels continuously with sync packets, like a serialized RGB bus. In command mode the panel has its own frame buffer and the host sends updates with DCS commands only when the image changes, which saves power. Short reaches only: a phone's flex, not a cable.

DSI uses the same D-PHY as CSI-2, pointed the other way. Lane 0 can turn around in low-power mode so the panel can answer register reads. The TE pin tells the host when the panel is scanning, so command-mode updates do not tear.

Critical design considerations

DisplayPort / eDP

Area	Consideration	Why (physics)	Rule of thumb
SI	Loss budget at HBR2/HBR3	Nyquist 2.7 / 4.05 GHz; FR-4 loss rises fast above 3 GHz	Short, low-loss routing; back-drill or avoid via stubs; retimer for long or connector-heavy paths; simulate with the channel model.
SI	AC-coupling capacitors	Cap pads are wider than the trace: a capacitive dip in impedance	0201 or 0402 caps, symmetric on P and N, plane voided under pads; place at the source end per the spec.
SI	Skew	Intra-pair skew adds common mode; inter-lane skew must fit the sink's deskew buffer	Intra-pair within ~0.1 mm; inter-lane is relaxed (sink aligns lanes) but follow the SoC limit.
SI	AUX channel	Training depends on AUX; a weak AUX means no link at all	Route as a 100 Ω pair, AC-coupled, with the specified pull-up/pull-down biasing.
PI	PHY and PLL rails	Jitter from supply noise reduces CDR margin	Dedicated filtered rails; follow the SoC's ripple limits.
EMC	Spread-spectrum clocking	A fixed link rate concentrates energy in narrow spectral lines	Enable downspread (≤ 0.5%) where both ends support it.
Other	Panel power sequencing (eDP)	Panel timing requires VDD → AUX/HPD → link → backlight, and the reverse at power-down	Implement T1–T12 delays from the panel datasheet; backlight last on, first off.

MIPI DSI

Area	Consideration	Why (physics)	Rule of thumb
SI	Mixed LP/HS signaling	LP mode is 1.2 V single-ended, unterminated; HS is ±200 mV terminated	Keep traces and flex short; do not add series resistors or external termination; 100 Ω differential routing.
SI	Lane skew to clock	Forwarded DDR clock: data is sampled against the clock lane	Match data lanes to the clock lane per the SoC guide.
PI	Panel supplies	Panel driver ICs need several rails (IOVCC, VCI, AVDD, VGH/VGL)	Follow the power-on order; supply noise shows up as flicker or lines.
Other	Tearing	Updating the frame buffer while the panel scans it shows a split image	Wire TE and synchronize command-mode writes to it.