Page 4 · Open-drain differential

HDMI

How HDMI turns pixels into TMDS symbols on four pairs, why the sink sets the voltage levels, what HDMI 2.1 changed, and the pins and parts between the SoC and the connector.

OwnerHDMI Forum / HDMI Licensing

Lanes3 TMDS data + 1 TMDS clock; HDMI 2.1 FRL: 4 data lanes, no clock

Rate per lane1.4: 3.4 Gb/s · 2.0: 6 Gb/s · 2.1 FRL: 3–12 Gb/s

SidebandDDC (I²C: EDID, SCDC, HDCP), HPD, CEC, +5 V

How it works

HDMI carries the same pixel stream as the old DVI interface, plus audio and metadata in packets sent during blanking. Through HDMI 2.0, three data lanes carry 8-bit values (one color component each) and a fourth pair carries a clock.

TMDS (Transition-Minimized Differential Signaling) in its DC-coupled form. The source only sinks current; the voltage levels come from the sink's 50 Ω pull-ups to 3.3 V. That is why an HDMI source must tolerate 3.3 V on its output pins, and why a sink that is powered off can back-power a source through them.

TMDS coding: 8 bits become 10

Minimize transitions. Each 8-bit value is converted with XOR or XNOR chaining, whichever produces fewer transitions, and a ninth bit records the choice. Fewer edges mean less high-frequency energy on the cable.
Balance DC. The encoder tracks the running count of 1s and 0s. If adding this word would push the balance further, it inverts the word and sets a tenth bit. The average stays near zero, so the receiver's threshold does not drift.
Control and data islands. During blanking, four special high-transition 10-bit words carry HSYNC, VSYNC and control; they also let the receiver find word boundaries. Audio and InfoFrames ride in "data islands" coded with TERC4.

TMDS bit rate = 10 × TMDS clock 1080p60: 148.5 MHz × 10 = 1.485 Gb/s per laneHDMI 1.4 tops out at a 340 MHz clock (3.4 Gb/s per lane). HDMI 2.0 goes to 6 Gb/s per lane by sending the clock at one quarter of the usual rate and scrambling the data to spread its spectrum (lower EMI).

HDMI 2.1 Fixed Rate Link

For 4K120 and 8K, HDMI 2.1 replaces TMDS with FRL: the clock pair becomes a fourth data lane, the clock is embedded, data is packed with 16b/18b coding, and lanes run at 3, 6, 8, 10 or 12 Gb/s (up to 48 Gb/s total), with optional Display Stream Compression. The physical layer behaves like a modern SerDes: equalization and link training, coordinated through registers the source reads and writes over DDC (SCDC).

Pins from processor to connector

A typical SoC-to-connector chain. A companion chip (for example TI's TPD12S016 class) provides ESD protection, the 5 V-to-SoC level shifting for DDC, CEC and HPD, and the current-limited 5 V supply in one part. Higher-rate designs add a redriver or retimer next to the connector.

Bring-up sequence

+5 V and HPD. The source drives +5 V on pin 18. The sink uses it to power its EDID memory and pulls HPD (pin 19) high to say "I am here, my EDID is readable".
Read EDID over DDC. I²C at 100 kHz, address 0xA0: supported resolutions, timings, color formats, audio.
HDCP (if protected content). Authentication messages over DDC, then the TMDS stream is encrypted.
SCDC for HDMI 2.0/2.1. The source writes the scrambling and clock-ratio bits (2.0) or runs FRL link training (2.1) through SCDC registers.
Video. TMDS or FRL lanes start; the sink locks and displays.

Critical design considerations

Area	Consideration	Why (physics)	Rule of thumb
SI	Impedance	100 Ω differential through PCB, ESD part, connector and cable; reflections close the eye at 3–6 Gb/s	100 Ω ± 10% routing; void the plane under connector and ESD pads; minimize vias; no stubs.
SI	Insertion loss and eye at the connector	Skin and dielectric loss grow with frequency; 6 Gb/s has its fundamental at 3 GHz	Keep SoC-to-connector short; add a redriver or retimer at HDMI 2.0/2.1 rates or long traces; check compliance eye at TP1.
SI	Intra-pair and lane skew	Intra-pair skew creates common mode and closes the eye; lane-to-lane skew must stay within the sink's deskew range	Intra-pair match ~0.1 mm; inter-pair a few mm is acceptable (sink deskews), keep clock lane matched per the SoC guide.
SI	ESD capacitance	Shunt C at 3 GHz is a low reactance: 0.5 pF ≈ 106 Ω	Ultra-low capacitance arrays (≤ 0.5 pF for 2.0/2.1) in flow-through layout at the connector.
PI	TMDS termination supply	The sink's 3.3 V pull-ups set the levels; source must tolerate 3.3 V on its pins	If the SoC PHY cannot accept 3.3 V, use an AC-coupled design with a level-shifting redriver.
PI	PHY PLL supply	Supply noise becomes jitter on TMDS clock and data	Isolated, low-noise PLL rail per the SoC hardware guide.
EMC	Radiated emissions from the cable	Common-mode current on the cable shield is an efficient antenna	Common-mode chokes on TMDS pairs if needed (they add insertion loss), connector shell bonded to chassis, scrambling on 2.0+.
Other	5 V supply and back-powering	A powered sink can back-feed 3.3 V through the TMDS terminations into an unpowered source	Current-limited +5 V (≥ 55 mA, short-protected); back-drive protection in the companion chip or PHY.
Other	DDC bus	Long cable adds capacitance; 5 V pull-ups at the connector side	Level shifter between SoC I/O and 5 V DDC; pull-up values per spec; keep source capacitance low.