Interface primer

FPD-Link Primer

FPD-Link is Texas Instruments' family of serial links for cameras and displays. It grew from a 1996 LVDS display interface into a single-coax link carrying video, control, clock and power. This primer follows that path from first principles.

OwnerTexas Instruments (National Semiconductor until 2011); proprietary

MediumOne coax or shielded twisted pair (III, IV)

ForwardIII: up to 4.16 Gb/s (UB953) · IV: 7.55 Gb/s line, 6 Gb/s video (UB971)

Back channel50 Mb/s (UB953) · 47.19 Mb/s (UB971), on the same wire

Also carriesPower (PoC), I²C, GPIO, frame sync, reference clock

InterfacesCSI-2, parallel DVP, DSI, HDMI, OpenLDI at the ends

What it is

FPD-Link (Flat Panel Display Link) is TI's family of serializers and deserializers. It began in 1996 as the LVDS link between a laptop's graphics chip and its LCD panel. In cars it became one of the two dominant ways, with GMSL, to carry camera and display video over a harness. The modern parts (FPD-Link III and IV) do the same job as GMSL: a serializer takes CSI-2 from a sensor and sends it down one coax; a deserializer hub on the compute board turns up to four links back into CSI-2 for the SoC, while control and power go back the other way on the same wire.

Each generation solved the next physical limit: first EMI and pin count inside a laptop display, then skew and pair count, then the need for control and power on the same wire, then bandwidth. Years are approximate.

The same three-in-one wire as any automotive SerDes. The FPD-Link signature is the back channel: besides I²C and GPIO it carries the deserializer's reference clock, so in synchronous mode the serializer, and through CLK_OUT the sensor, run on the ECU's crystal.

Why a SerDes at all

Limit of a board-level interface on a harness	Physics	FPD-Link answer
Ground offset between the two ends	Harness return current × resistance gives volts of DC difference	AC coupling with DC-balanced coding
High-frequency loss	Skin effect (∝ √f) and dielectric loss (∝ f) attenuate the edges	Adaptive receive equalization
Skew between parallel pairs	Different pairs have slightly different propagation delay, which accumulates with length	One serial lane with an embedded clock and CDR
Wire count	Four data pairs + clock pair + I²C + power	Everything on one center conductor and shield
Clock coherence across cameras	Separate crystals drift by tens of ppm, so frames slip relative to each other	Reference clock sent over the back channel (synchronous mode)

Generations

	FPD-Link (I)	FPD-Link II	FPD-Link III	FPD-Link IV
Wires	3–4 data pairs + clock pair	1 pair	1 coax or STP	1 coax or STP
Clock	forwarded on its own pair	embedded	embedded	embedded
Rate	~0.6 Gb/s per pair (7 × pixel clock)	~1 Gb/s class	up to 4.16 Gb/s (UB953)	7.55 Gb/s line, 6 Gb/s video (UB971)
Back channel	none	none	yes, ~50 Mb/s on UB953	47.19 Mb/s
Power over cable	no	no	yes	yes
Where you see it	inside displays (OpenLDI)	older automotive	most current automotive cameras and displays	high-resolution cameras

The original FPD-Link became the OpenLDI standard and still appears as the "LVDS" input of many LCD panels. Modern FPD-Link III display deserializers often output OpenLDI to the panel's timing controller, so both ends of the family can sit on one board.

The pages

PhysicsLVDS current steering, 7:1 serialization and skew, embedded clocking, channel loss and equalization, the back channel, power over coax. Link & clockingSynchronous vs non-synchronous clocking and the PLL behind it, packets, virtual channels, I²C aliasing, GPIO, diagnostics. Cameras & displaysHub architecture, frame sync, display chain to OpenLDI, bandwidth math, GMSL comparison, design and debug.

The one-minute answer

If asked "how does FPD-Link work?"

It's TI's SerDes family. It started as LVDS 7:1 for display panels: 3.5 mA current-steered into 100 Ω for 350 mV swings, seven bits per pair per pixel clock. Modern FPD-Link III and IV serialize everything onto one coax with an embedded clock: the serializer takes CSI-2, sends it at up to 4.16 Gb/s (III) or 7.55 Gb/s (IV); the deserializer equalizes the cable, recovers the clock and rebuilds CSI-2. A ~50 Mb/s back channel on the same wire carries I²C, GPIO and frame sync, and in synchronous mode the deserializer's reference clock too, so every camera is frequency-locked to the ECU. Power rides on the center conductor through a bias-T. A hub like the UB960 merges four cameras onto CSI-2 by virtual channel.