Page 4 · Putting it to work

Cameras and Displays

The full camera path through a hub, display chains, bandwidth sizing, how FPD-Link compares with GMSL and A-PHY, and how to design and debug it.

Camera to processor

Power and lock. The ECU enables PoC. The camera's regulators start, the serializer powers up and the link locks: back channel first, then the forward channel at the rate set by the reference clock.
Configure. The SoC programs the hub over local I²C (port enables, aliases, VC mapping), then programs each sensor through its alias over the back channel.
Clock and sync. In synchronous mode, each sensor runs on CLK_OUT derived from the ECU's crystal. A FrameSync pulse from the hub, sent as a back-channel GPIO, starts exposures together.
Stream. Each sensor sends CSI-2; the serializer checks and wraps it and drives the cable. The hub equalizes, recovers, checks CRC, remaps VC, and outputs CSI-2.
Into memory. The SoC's CSI-2 receiver sorts by VC into per-camera buffers for the ISP.

Each camera sends on VC 0. The hub assigns each port a different VC and interleaves the lines on one CSI-2 port, optionally replicating it on a second port.

Bandwidth math

Camera	Raw rate	~10% overhead	Fits on
2 MP (1920×1080) RAW12, 60 fps	1.49 Gb/s	~1.6 Gb/s	FPD-Link III 4.16 Gb/s
4 MP (2560×1600) RAW12, 30 fps	1.47 Gb/s	~1.6 Gb/s	FPD-Link III 4.16 Gb/s
8 MP (3840×2160) RAW12, 30 fps	2.99 Gb/s	~3.3 Gb/s	FPD-Link IV (6 Gb/s video)
4 × 2 MP at 60 fps into one hub	6.0 Gb/s	~6.6 Gb/s	CSI-2 output: 4 lanes ≥ 1.65 Gb/s each

TI positions the UB953 for 2 MP at 60 fps or 4 MP at 30 fps, along with satellite radar, lidar and time-of-flight sensors. The serializer's CSI-2 input is the other limit: the UB971 accepts up to 1.5 Gb/s per lane, 6 Gb/s per port.

Displays

A typical display path. The panel end converts back to the original LVDS FPD-Link, so the family's first and current generations meet on the same board.

FPD-Link vs GMSL vs A-PHY

	FPD-Link III / IV	GMSL2 / 3	MIPI A-PHY
Vendor	TI only	ADI only	Open standard, several vendors
Forward rate	4.16 / 7.55 Gb/s	3–6 / 12 Gb/s	up to 16 Gb/s (v1.0), 32 Gb/s (v1.1)
Back channel	~50 Mb/s	187.5 Mb/s	up to ~200 Mb/s
Clock to camera	ref clock over back channel (sync mode)	reference over reverse on newer parts	implementation-specific
Medium	coax or STP, PoC	coax or STP, PoC	coax or STP, PoC
Lock-in	both ends TI	both ends ADI	mix vendors

The physics is the same for all three. The practical choice is the ecosystem: which serializers the camera modules you can buy already contain, which hubs the SoC vendor's reference designs use, and second-source risk. On a robot that chooses its own cameras, that is usually decided by the module supplier.

Board design checklist

Controlled-impedance trace (50 Ω coax, 100 Ω differential for STP) from the pin to the connector, short, on one layer, ground-stitched.
Remove the reference plane under wide pads (AC capacitor, connector) to avoid capacitive dips in impedance.
Low-capacitance ESD at the connector.
PoC: inductor chain with the GHz element next to the signal node; check impedance across the band at full DC current.
Separate, quiet PLL supplies; follow the datasheet's ripple limits.
Run the vendor's channel and PoC analysis, then measure insertion and return loss with a VNA.

Debug order

Power at the camera. Serializer voltage monitor or a probe. Dips under load mean PoC drop or inductor saturation.
Back channel first. If the SoC cannot reach the serializer over I²C, the back channel is down: cable, connector, line fault.
Forward lock and CRC. Read lock status, EQ settings, CRC counters. Heat, cool and flex the cable while watching them.
Pattern generator. Enable the serializer's test pattern. If the pattern arrives clean, the problem is on the sensor side.
CSI-2 configuration. Lane count, data rate, data type and VC mapping must agree between sensor, serializer, hub and SoC.

Questions to practice

Why does LVDS use a current source?

Constant current means the supply current never changes with data, so there is no di/dt on the rails, little ground bounce and little EMI. The voltage swing is simply I × R_termination, 3.5 mA × 100 Ω = 350 mV.

Why couldn't the original FPD-Link go to a camera 5 m away?

Clock and data travel on separate pairs, and pair-to-pair skew on a long cable exceeds the 1–2 ns bit slot. It is also DC-coupled with a limited common-mode range, and needs ten wires.

What is synchronous mode and why use it?

The deserializer sends its reference clock over the back channel; the serializer's PLL locks to it and outputs a sensor clock. Every camera is then frequency-locked to one ECU crystal, so frames never drift relative to each other. FrameSync then aligns their phase.

How do four identical sensors share one I²C bus?

Address aliasing in the deserializer: each port gets a unique alias that is translated to the sensor's real address on the far side.

How is the back channel separated from the forward channel?

Mostly by frequency, since it is ~80× slower, plus subtraction of each transceiver's own transmit signal where the spectra overlap.

FPD-Link or GMSL for a new robot camera?

Same physics and similar capability. Decide on the camera modules available, the SoC reference designs, rate headroom for future sensors, diagnostics needed for the safety case, and second-source exposure, since each locks both ends to one vendor.