Page 2 · From LVDS to a single coax

FPD-Link Physics

Why LVDS uses a current source, why parallel pairs stop working on a harness, and how one coax ends up carrying an embedded clock, a back channel and power.

FPD-Link's history is a sequence of physics problems, each solved in turn. Following it in order is the fastest way to understand what the modern parts do.

1. LVDS: moving bits with a constant current

The original problem was inside a laptop: send 24-bit color at tens of MHz from the graphics chip, through the hinge, to the panel, without radiating noise into the radio and without dozens of wires. Single-ended CMOS swings 3.3 V rail to rail. Every edge charges the line capacitance and dumps a current spike, I = C·dV/dt, into the supply and ground. LVDS (Low-Voltage Differential Signaling, TIA/EIA-644) fixes that with three ideas.

An LVDS driver is a constant current source steered through an H-bridge. The data only changes which direction 3.5 mA flows through the 100 Ω termination at the receiver, which makes ±350 mV. Simplified schematic.

Constant current. The driver always draws 3.5 mA; data only changes its direction. Supply current never steps, so there is no di/dt on the power rails and almost no ground bounce.
Small swing. 350 mV instead of 3.3 V: about 10 times less charge moved per edge, faster edges for the same current, less radiated energy.
Differential. The two wires carry equal and opposite currents. Their magnetic fields cancel a short distance away, so a tightly coupled pair barely radiates. External noise couples onto both wires equally and the receiver ignores it: it only looks at the difference, with a ±100 mV threshold and a common-mode range of roughly 0 to 2.4 V, so about ±1 V of ground shift is tolerated.

P_driver ≈ 3.5 mA × V_DD V_diff = 3.5 mA × 100 Ω = 350 mVPower is set by the current, not by the data rate, which is why LVDS is efficient at high rates and wasteful when idle.

2. 7:1 serialization and the skew wall

To save pins, FPD-Link serializes 7 bits per pair in each pixel clock and sends the clock on its own pair. Four data pairs carry 28 bits: 24-bit RGB plus the three sync signals.

Original FPD-Link / OpenLDI: each pixel clock, every data pair shifts out 7 bits. Four pairs give 28 bits per pixel. The clock pair runs at the pixel rate with a 4:3 duty pattern so the receiver can find the bit boundaries. Bit order shown follows the common VESA 24-bit mapping; panels vary.

bit rate per pair = 7 × f_pclk 85 MHz → 595 Mb/s → 1.68 ns per bitThe receiver multiplies the clock by 7 with a PLL and samples each pair in the middle of each slot. Every source of skew between a data pair and the clock pair eats into that 1.68 ns.

On a PCB or a short flex, pair-to-pair skew is tens of picoseconds and the scheme works. On a vehicle harness it fails: pairs in a cable differ in length and dielectric, skew grows with every meter, the cable smears edges, and there is no DC tolerance. It also needs ten wires. That is the limit FPD-Link II removed.

3. One pair, clock embedded

Put everything on one pair and there is nothing for the data to skew against. The receiver has to find the bit timing from the data itself, using a clock-and-data-recovery (CDR) loop: a PLL whose phase detector compares data transitions with its own clock edges and steers the sampling point to the center of the eye. That requires two guarantees from the data.

The classic embedded-clock idea used from FPD-Link II on: wrap each word with a fixed 1 and 0 so a known edge appears at every word boundary, and add a flag that inverts the word when that keeps the running disparity near zero. Real FPD-Link III/IV framing is more elaborate and adds scrambling, but it solves the same two problems: a timing reference for the CDR and a zero average for the AC coupling.

Transitions. The CDR can only correct its phase on an edge. Long runs of identical bits let it drift. A fixed edge per word (or scrambling) bounds the time between edges.
DC balance. The link is AC-coupled so that ground offset and, later, DC power do not reach the receiver. AC coupling is a high-pass filter: a stream that averages more 1s than 0s shifts the baseline and moves the decision threshold. A balancing flag or a scrambler keeps the average at zero.

4. The harness is a lossy transmission line

At GHz rates, a 50 Ω coax or 100 Ω twisted pair is many wavelengths long. Two loss mechanisms grow with frequency: skin effect, where current crowds into a layer δ = √(ρ / πfμ) deep (1.2 µm in copper at 3 GHz), giving loss ∝ √f; and dielectric loss ∝ f·tan δ.

Illustrative 15 m automotive coax, scaled so loss at 3 GHz is about 21 dB. The dashed curve is the √f skin-effect term; the solid curve adds dielectric loss, which grows linearly with frequency.

The frequency that matters is Nyquist, half the bit rate for two-level signaling: 2.08 GHz for 4.16 Gb/s. A single 1 bit arrives late, low and stretched across several bit periods; its tail lands on the next bits (intersymbol interference). The deserializer's adaptive equalizer undoes this: a continuous-time stage with rising gain toward Nyquist restores the edges, and decision feedback subtracts the remaining tails using bits already decided. It adapts at link-up, so the same part works across different cable lengths and temperatures.

5. The back channel

FPD-Link III's main addition is a bidirectional control channel on the same conductor: about 50 Mb/s from deserializer to serializer on the DS90UB953, 47.19 Mb/s on the FPD-Link IV DS90UB971. Two signals going in opposite directions on a linear line simply add. Each end separates them in two ways.

Approximate spectral occupancy for a UB953-class link. The back channel is about 80 times slower than the forward channel, so most of its energy lies decades below the forward channel's. The two directions still overlap a little, so the transceivers also subtract their own transmitted signal. Band edges are illustrative.

Frequency. The back channel is roughly 80 to 160 times slower than the forward channel. Its energy sits mostly below ~50 MHz; the forward channel's sits up near GHz. Filters do most of the separation.
Cancellation. Each transceiver knows the waveform it is sending and subtracts it from what it sees at the pin, leaving the far end's signal. Reflections from a mismatched connector are copies of its own signal arriving later, which the canceller only partly removes. That is why return loss matters as much as insertion loss.

6. Power over coax

Camera power is fed onto the center conductor at the ECU and taken off at the camera through a bias-T: a series capacitor passes the signal into the PHY and blocks DC; an inductor network passes DC to the load and must look like an open circuit across the signal band. A shunt impedance Z across the line (seen as 25 Ω, the source and load in parallel) costs S₂₁ = 2Z/(2Z + Z₀). At Z = 1 kΩ that is 0.2 dB; at 200 Ω, 1 dB.

The low edge is set by the back channel, the lowest-frequency signal on the wire. |Z| = 2πfL: 1 kΩ at 2 MHz needs about 80 µH.
Every inductor turns capacitive above its self-resonant frequency, so a large inductor is combined with smaller ones and a ferrite to cover up to several GHz.
DC current lowers inductance as the core approaches saturation; rate the parts for the camera's peak and inrush current.
Cable and inductor resistance drop volts. Send a higher voltage (often 9–12 V or more) and regulate in the camera.

7. From noise to error rate

BER = ½ · erfc(Q/√2) Q = (eye half-height) / σ_noise Q ≈ 7 → 10⁻¹²At 4.16 Gb/s, 10⁻¹² is about one error every four minutes. FPD-Link adds CRC on its own packets and checks CSI-2 ECC and checksums, so every error is detected and counted even when it cannot be corrected.

Thirty-second version

LVDS steers a constant 3.5 mA through 100 Ω for quiet, low-swing differential signaling. Parallel LVDS hits a skew wall on long cables, so FPD-Link II/III serialize onto one pair with an embedded clock, DC-balanced for AC coupling. The cable loses high frequencies, so the receiver equalizes adaptively. A slower back channel shares the wire by frequency separation and echo cancellation, and power rides on the center conductor through a bias-T.