Page 3 · Protocol and timing

Link and Clocking

How FPD-Link locks every camera to one crystal, what each direction carries, and how one SoC configures four identical sensors.

Clocking: the FPD-Link signature

A camera system has several clocks: the sensor's pixel clock, the serializer's line rate, the deserializer's recovered clock and the SoC's frame timing. If each camera has its own crystal, they differ by tens of ppm. At 30 fps, a 50 ppm difference is a drift of 1.5 ms per minute between two cameras, so their frames slide past each other. FPD-Link offers clocking modes to control this. The DS90UB953 datasheet lists four: synchronous, non-synchronous external clock, non-synchronous internal clock, and DVP backwards-compatible.

Phase detectorcompare edgesLoop filtersets bandwidthVCOf_out÷ Ndividerf_out = N · f_reff_ref from back channel (sync) or a local crystalForward linkserializer TXCLK_OUTto image sensor
A phase-locked loop multiplies a reference frequency by N. The phase detector compares the divided VCO output with the reference and the loop filter steers the VCO until they match in phase. In synchronous mode the reference arrives over the back channel, so the forward line rate and the sensor clock are exact multiples of the ECU's crystal.
ModeWhere the reference comes fromUse it when
SynchronousThe deserializer's reference, sent over the back channel. The serializer's PLL locks to it; CLK_OUT feeds the sensor.Multi-camera systems that must be frequency-locked to one ECU crystal. No crystal on the camera.
Non-synchronous, externalA local clock on the camera boardThe sensor already has its own required clock, or the back channel is not trusted for timing
Non-synchronous, internalThe serializer's internal oscillatorSimplest single-camera designs where frequency lock does not matter
DVP compatibilityThe parallel sensor's pixel clockOlder parallel-output sensors and earlier FPD-Link III deserializers

PLL physics in one paragraph. The loop bandwidth decides which jitter wins. Below the bandwidth, the output follows the reference: a clean ECU crystal improves the camera, a noisy back-channel recovery degrades it. Above the bandwidth, the VCO's own noise dominates. Supply noise on the PLL rail modulates the VCO frequency directly, which is why the datasheet gives separate, tightly filtered PLL supplies.

What travels on the forward channel

A UB953-class serializer receives CSI-2 from the sensor on up to four D-PHY lanes, checks the CSI-2 ECC and checksum, and repacks the packets into the FPD-Link stream with its own CRC. The deserializer checks that CRC, reconstructs the CSI-2 packets and forwards them. FPD-Link IV parts carry up to 16 CSI-2 virtual channels and support multi-exposure HDR data types.

Forward channel contentPurpose
CSI-2 packets (long and short)Video lines, frame and line markers, embedded sensor data
I²C read data and ACKsReplies to register accesses from the SoC
GPIO statesSensor interrupts, error flags
Status and diagnosticsVoltage, temperature, lock and error information
Back channel contentPurpose
Reference clock (synchronous mode)Frequency-locks serializer and sensor to the ECU
I²C writes and read requestsConfigure the sensor and serializer
GPIO statesFrame sync, reset, power-down

Control: I²C over the link

SoCI²C masterDeserializeralias tableSerializer, port 0SensorID 0x1ASerializer, port 1SensorID 0x1ASerializer, port 2SensorID 0x1ASlaveAlias 0x30 on port 0 → SlaveID 0x1ASlaveAlias 0x32 on port 1 → SlaveID 0x1A
The SoC addresses each remote sensor by an alias. The deserializer matches the alias, forwards the transaction over that port's back channel, and the serializer replays it on its local I²C bus with the real address. Replies return on the forward channel; SCL is stretched while the round trip happens.

Identical cameras have identical I²C addresses. The deserializer's alias table gives each remote device a unique address on the SoC's bus, which is why one I²C bus from the SoC can configure four identical sensors.

Hubs and virtual channels

A quad hub such as the DS90UB960 (FPD-Link III) or DS90UB9702 (III and IV) receives four links. Each receive port can rewrite the CSI-2 virtual channel ID, so four cameras that all send on VC 0 arrive at the SoC on VC 0–3. The hub interleaves their packets onto its CSI-2 output ports or replicates one stream onto both ports, for example to feed a safety processor alongside the main SoC.

Diagnostics

FeatureWhat it catches
CSI-2 ECC, checksum and D-PHY error detection on the serializerErrors between the sensor and the serializer, before the cable
Link CRC on the forward channelErrors in the cable and connectors
Lock status and adaptive EQ read-backLink instability; a change in cable loss
Line-fault detection (UB971)Open cable, short to ground
Voltage and temperature measurementPoC sag, supply faults, thermal problems at the camera
Pattern generator and BISTTest the link and the SoC receiver without a working sensor
I²C write protection (UB971)Stray writes corrupting camera configuration
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