Interface primer

MIPI CSI-2 Primer

CSI-2 is the standard way a sensor streams data into a processor: a one-way, source-synchronous serial link with a small packet protocol on top. It was built for phone cameras. It now carries automotive cameras, ToF sensors and the raw ADC output of radar chips such as the AWR2243.

OwnerMIPI Alliance, Camera Working Group

DirectionSensor → host only; control on a separate I²C-style bus

PHYD-PHY (clock + 1–4 lanes) or C-PHY (1–3 trios)

Lane rateD-PHY 80 Mb/s to 2.5 Gb/s (v1.2), 4.5 Gb/s (v2.x)

ReachA board or short flex, roughly 30 cm or less

Integrity6-bit ECC on every header, CRC-16 on every payload

What it is

CSI-2 stands for Camera Serial Interface, second generation. It replaces the old parallel camera bus (8 to 16 data pins, a pixel clock, HSYNC and VSYNC) with a few low-swing differential lanes. The sync signals turn into packets: a Frame Start packet replaces the VSYNC edge, and a line of pixels travels as one long packet with a header and a checksum.

The specification is split in two. The CSI-2 protocol defines packets, data types, virtual channels and how bytes are spread across lanes. The PHY is a separate MIPI specification: D-PHY for most designs, C-PHY for high-bandwidth phone cameras. CSI-2 runs on either one. A third piece, CCI (Camera Control Interface), is an I²C-compatible bus the host uses to program the sensor's registers.

Each layer on the transmitter has a peer on the receiver. Only the PHY crosses the wire; everything above it is logic. Image data moves one way. Control (CCI) goes the other way on a separate, slow bus.

Why engineers use it

Pins and power. Four D-PHY lanes plus a clock carry up to 10 Gb/s on 10 wires at about 200 mV swing. A parallel bus would need far more pins and more power for the same rate.
Low-power idle. Between packets the lanes drop to 1.2 V CMOS levels with no termination current. Blanking time costs almost nothing.
Ecosystem. Most application processors, ISPs and SoCs (NVIDIA Jetson, TI Jacinto, NXP i.MX, Qualcomm) have hard CSI-2 receivers. A sensor with a CSI-2 port connects to them without glue logic.
Built-in framing and checking. The receiver knows where frames and lines begin, what format the payload is, and whether any byte was corrupted.

What it is not

Not a cable interface. D-PHY is DC-coupled and depends on 1.2 V single-ended LP signaling, so it cannot cross a long harness. In a vehicle, CSI-2 is carried over coax by a SerDes such as GMSL, FPD-Link III/IV or MIPI A-PHY, and comes back out as CSI-2 at the far end.
Not bidirectional. Data only flows from sensor to host. There is no acknowledge and no retransmit. A CRC error is counted and the line is dropped.
Not self-configuring. The receiver has to be told the lane count, lane rate, data type and line length. If the host's settings do not match the sensor's, nothing useful arrives.

The pages

ProtocolPackets, header, ECC and CRC, data types, virtual channels, lane striping, CCI. D-PHY signalingLP and HS voltage levels, the start-of-transmission sequence, timing, termination, clock modes. D-PHY vs C-PHY3-phase trios, embedded clock, 16-bit-to-7-symbol coding, and when each PHY fits. AWR2243How the radar maps chirps to lines, the payload, the bandwidth math, and the two-chip cascade. Zynq-7020Receiving CSI-2 without a hard D-PHY: resistor network, ISERDES clocking, packet parsing, DMA into DDR.

The one-minute answer

If asked "what is CSI-2?"

It's MIPI's sensor-to-processor streaming interface. Physically it's usually D-PHY: a forwarded DDR clock plus up to four data lanes, each about 200 mV differential at up to a couple of Gb/s, dropping to 1.2 V single-ended low-power states between bursts. On top of that it's a light packet protocol: a 4-byte header with virtual channel, data type, word count and ECC, then the payload, then a CRC-16. Frames and lines are marked with short packets. On our radar board the AWR2243 used it to stream raw ADC samples, one chirp per line, at 4 × 600 Mb/s into the Zynq, where a soft receiver built on ISERDES deserialized it and DMA'd it into DDR.