Page 3 · Signaling levels

D-PHY Signaling

Each D-PHY lane is a differential pair that switches between two completely different electrical modes: 1.2 V single-ended low-power (LP) signaling for control and idle, and roughly 200 mV differential high-speed (HS) signaling for data.

Two modes on one pair

	Low-power (LP)	High-speed (HS)
Signaling	Two independent single-ended wires, 1.2 V CMOS	Differential, SLVS-like, low swing
Levels	0 V or 1.2 V on each wire	Each wire 100–300 mV around a 200 mV common mode
Termination	None (high impedance)	100 Ω differential at the receiver, switched in
Data rate	Up to 10 Mb/s (escape mode)	80 Mb/s to 1.5 Gb/s (v1.1), 2.5 Gb/s (v1.2), 4.5 Gb/s (v2.x)
Used for	Idle (LP-11), entering and leaving HS, escape commands, ULPS	All CSI-2 packet data
Power	Near zero when static	Constant ~2–4 mA per lane while active

The four LP line states are written as Dp Dn: LP-11 is Stop (idle), LP-01 is HS-Request, LP-00 is Bridge, LP-10 starts an escape-mode request. A lane sits in LP-11 whenever it has nothing to send.

Electrical levels

Parameter	Symbol	Value
LP transmitter / receiver
Output high	VOH	1.1 – 1.3 V
Output low	VOL	−50 – 50 mV
Input high threshold	VIH	≥ 880 mV
Input low threshold	VIL	≤ 550 mV
HS transmitter
Common-mode voltage	VCMTX	150 – 250 mV (200 typ)
Differential output, \|Dp − Dn\|	\|VOD\|	140 – 270 mV (200 typ)
Single-ended output high	VOHHS	≤ 360 mV
Single-ended output impedance	ZOS	40 – 62.5 Ω
HS receiver
Common-mode input range	VCMRX	70 – 330 mV
Differential threshold	VIDTH / VIDTL	±70 mV (v1.1; tightened to ±40 mV at lower rates in later revisions)
Differential termination	ZID	80 – 125 Ω

So a "1" in HS mode is Dp ≈ 300 mV and Dn ≈ 100 mV: +200 mV differential. A "0" swaps them. The swing depends on the receiver's termination: the transmitter's ~50 Ω source impedance and the 100 Ω load form a divider. Without the termination, the lines would swing to roughly twice that, so the termination is part of the level definition, not only a reflection fix.

Starting and ending a burst

One HS burst on one data lane, drawn to voltage scale. The lane leaves LP-11 through LP-01 and LP-00, the receiver switches in its 100 Ω termination, and the lines collapse to the 200 mV common level. The transmitter sends HS-0, then the sync byte (00011101 on the wire, LSB first), then data. At the end it holds the inverse of the last bit (trail) and returns to LP-11.

LP-11 → LP-01. The transmitter drives Dp low. This is the request to enter HS. It must last at least TLPX (50 ns).
LP-01 → LP-00. Dn goes low too. Seeing LP-00, the receiver enables its 100 Ω termination and its HS receiver.
HS-PREPARE, HS-ZERO. The transmitter starts driving HS levels with a constant differential 0. The receiver ignores the line for HS-SETTLE while its termination and input settle.
Sync byte. The transmitter sends 0xB8, which on the wire is 00011101 (LSB first). The receiver searches the bit stream for it. Where it lands sets the byte boundary for the rest of the burst.
Payload. Packet bytes, LSB first, at one bit per UI. UI = 1 / line rate, and the bit clock is the DDR clock lane, so a 600 Mb/s lane uses a 300 MHz clock.
HS-TRAIL, then LP-11. The transmitter holds the inverse of the last bit for HS-TRAIL, then releases the line to LP-11. The receiver disables termination and discards the trail.

Timing that matters

Parameter	Requirement	Why it exists
TLPX	≥ 50 ns	Minimum time in any LP state, so a 1.2 V CMOS receiver can see it.
THS-PREPARE	40 ns + 4 UI to 85 ns + 6 UI	LP-00 to HS driving. Gives the receiver time to switch termination.
THS-PREPARE + THS-ZERO	≥ 145 ns + 10 UI	Lets the HS receiver settle before the sync byte.
THS-SETTLE (RX)	85 ns + 6 UI to 145 ns + 10 UI	Window the receiver ignores after LP-00. Often a register in the receiver. Set it wrong and the first byte is garbage.
THS-TRAIL	≥ max(8 UI, 60 ns + 4 UI)	Holds the line after the last bit so the last bit is captured cleanly.
TCLK-PREPARE + TCLK-ZERO	≥ 300 ns	Clock lane equivalent of HS-PREPARE + HS-ZERO.
TCLK-PRE	≥ 8 UI	Clock running before the data lanes start their SoT.

Add up the LP-to-HS entry (TLPX × 2 + HS-PREPARE + HS-ZERO) and the exit (HS-TRAIL + HS-EXIT ≥ 100 ns) and each burst costs roughly 0.4–0.6 µs of overhead that carries no data. At 600 Mb/s a 4 KB packet on four lanes takes about 14 µs, so the overhead is a few percent. At 2.5 Gb/s with short lines it can be 20% or more.

The receiver front end

The same two wires feed three receivers. The LP receivers watch each wire as 1.2 V logic to find the LP-11 → LP-01 → LP-00 entry. The termination is switched in only during HS, otherwise it would load the LP drivers down to ~0 V. This switch is what most FPGAs lack.

A D-PHY receiver needs three things on the same two pins: two 1.2 V CMOS input buffers, a differential receiver that resolves ±70 mV around a 200 mV common mode, and a 100 Ω termination that turns on and off within a few tens of nanoseconds. SoCs build this as a hard macro. FPGAs generally have one or two of these pieces but not all three on one pin, which is why the Zynq page needs an external network.

D-PHY cannot be AC-coupled. LP signaling is DC levels with no transitions guaranteed, and the HS common mode is part of the spec. Series capacitors would break both.

The clock lane

The clock lane is a forwarded DDR clock: data is sampled on both edges, and the clock edges are placed in the middle of the data eye (90° relationship). The receiver can clock data directly with it, with no clock-recovery circuit. This is why D-PHY receivers are simple and why they adapt to any rate in the allowed range.

Continuous clock mode. The clock lane stays in HS for the whole session; only the data lanes drop to LP between packets. Simpler for the receiver, a few mW more power. The AWR2243 uses this mode.
Non-continuous clock mode. The clock lane also drops to LP between bursts. Saves power, but the receiver's byte clock stops whenever the link idles. Any logic clocked by it, including FIFO write sides, must tolerate a clock that disappears.

Above 1.5 Gb/s, D-PHY v1.2 added a deskew sequence: the transmitter sends a known pattern so the receiver can calibrate per-lane delay, because fixed clock-to-data alignment no longer holds at those UI widths.

Escape mode and ULPS

From LP-11 a lane can enter escape mode with the sequence LP-10, LP-00, LP-01, LP-00, followed by an 8-bit command sent in LP using spaced-one-hot coding. Commands include Ultra-Low-Power State (ULPS), low-power data transmission, and triggers. CSI-2 uses ULPS to put the link to sleep. Low-power data and bus turnaround matter for DSI displays more than for cameras.

Board design checklist

100 Ω differential routing. Match P to N within a pair tightly, and match each data pair to the clock pair. Skew eats directly into the half-UI margin because the clock is forwarded.
Continuous reference plane under every pair. No stubs. No AC coupling caps.
Keep the LP path healthy too: series parts, ESD diodes and connectors must not pull LP-11 below the 880 mV VIH threshold.
Probe LP-11 at the receiver with a scope (should read ~1.2 V on both lines when idle) before trying to debug HS. Most bring-up failures are visible there.

Questions to expect

Why does D-PHY need both LP and HS modes?

HS needs constant termination current, about 2–4 mA per lane. Between packets and frames there is nothing to send, so the lane drops into 1.2 V CMOS levels with no termination and essentially zero static current. LP also gives a clean, slow, unambiguous way to signal "a burst is starting," which lets the receiver find the byte boundary without a continuous training pattern.

Why can't you just put a 100 Ω resistor across the pair?

In LP mode each wire is driven single-ended to 1.2 V or 0 V by a fairly weak driver. A 100 Ω resistor across the pair would short LP-01 and LP-10 states and pull LP levels below the VIH threshold. The termination has to be switched off in LP. Resistor-network FPGA solutions use a larger fixed value as a compromise.

What does the sync byte do?

The deserializer starts at an arbitrary bit phase. 0xB8 (00011101 on the wire) is a pattern that doesn't appear in the HS-ZERO preamble, so the receiver slides a window across the incoming bits until it matches. The offset where it matches is the byte boundary for the rest of the burst.

What does HS-SETTLE protect against?

When the receiver switches its termination in, the lines are moving from LP levels to HS levels and the HS comparator output is meaningless. HS-SETTLE masks that window. It scales with UI, so a receiver configured for 1.5 Gb/s while the link runs at 150 Mb/s can unmask too early and see a false sync.