Page 6 · Receiving it in an FPGA

Zynq-7020 CSI-2 Receiver

The Zynq-7000 family has no hard MIPI PHY and no CSI-2 controller. The receiver is built from general-purpose HR-bank I/O, an external resistor network, the SelectIO deserializers, and fabric logic. It works well at the AWR2243's 600 Mb/s per lane.

The public teardown photo shows the automotive XA7Z020 on the radar board, paired with 1 Gb of DDR3L on a 16-bit bus. The receiver itself uses a small fraction of the device; the fabric budget goes to the range FFT and data reduction that follow it. The design is the same on a 7010, which has about a third of the 7020's logic.

Why an external network is needed

A D-PHY receiver needs 1.2 V CMOS LP inputs, a differential HS receiver near a 200 mV common mode, and a termination that switches in and out within tens of nanoseconds. A 7-series HR bank can do the first two on separate pins at VCCO = 1.2 V, but it cannot switch its internal termination at run time, and its internal 100 Ω DIFF_TERM is only available when the bank runs at 2.5 V. So the termination and the HS/LP split move onto the board.

• Pins. About four FPGA pins per lane: an HS differential input plus LP inputs for Dp and Dn. A 4-lane link with clock is around 20 pins.
• I/O standards. LP inputs as HSUL_12 or LVCMOS12. HS input as a differential standard such as LVDS_25 with internal termination off, which 7-series allows in a bank whose VCCO is not 2.5 V. Confirm the combination for your bank in UG471.
• Termination. Fixed, so it is a compromise: low enough to control HS reflections, high enough that LP-11 still reaches the 880 mV VIH threshold. Intel's equivalent app note uses a fixed 300 Ω across the pair for the same reason. AMD's XAPP894 gives the 7-series topology and values.
• Option: skip LP on data lanes. With a continuous clock, some designs find bursts purely by sync-byte search on the HS input. Cheaper, but during LP-11 the HS input sees 0 V differential and can chatter, so false syncs must be filtered by a valid header ECC.

The datapath

1. Capture: IDELAY and ISERDES

Each lane's HS input goes through an IDELAYE2 (78 ps taps with the 200 MHz IDELAYCTRL reference) into an ISERDESE2 in DDR mode with a 1:8 ratio. The clock lane's HS input enters on a clock-capable pin (MRCC or SRCC) and drives two regional buffers:

• BUFIO at the bit clock: 300 MHz for 600 Mb/s. Clocks the ISERDES CLK input.
• BUFR divided by 4: 75 MHz. Clocks CLKDIV and all byte-wide logic. 75 MHz × 8 bits × 4 lanes = 2.4 Gb/s, which matches the link.

BUFIO and BUFR only reach their own clock region, so the clock lane and all four data lanes of one link must sit in the same bank and region. Two cascaded AWR2243s need two banks with their own clock-capable pins. On the 7020 in CLG400 that is banks 34 and 35, which also have to carry everything else in the PL.

D-PHY places the clock edge in the middle of the data eye, so in principle no delay is needed. In practice per-lane trace skew and the IBUFDS/BUFIO insertion delay shift the sampling point. Set IDELAY taps per lane, either fixed from a calibration sweep at bring-up or adjusted in the field by sweeping taps and watching the ECC error count.

600 Mb/s is well within the HR-bank ISERDES range on any speed grade. AMD's D-PHY IP lists 7-series throughput at line rates up to 1,250 Mb/s; check DS187 for the exact limit of your speed grade before going higher.

2. Burst detection and byte alignment

The LP inputs feed a small state machine per lane that detects LP-11 → LP-01 → LP-00 and starts an HS-SETTLE timer, counted in byte clocks. After the timer expires, a sync search looks at two consecutive deserialized bytes (16 bits) for 0xB8 at each of the eight bit offsets. The match offset drives either the ISERDES BITSLIP input or a barrel shifter in fabric. The lane then outputs aligned bytes until it returns to LP-11.

3. Lane merge

Lanes find sync on slightly different byte clocks. A shallow FIFO per lane absorbs that. Once all four lanes report sync, the merger reads one byte from each in lane order and outputs 32 bits per byte clock. When the word count says the packet has ended, it stops each lane at the right byte and ignores the trail.

4. Packet parser

• Check and correct the header ECC. Drop the burst on an uncorrectable header.
• Decode data type and virtual channel. Short packets become frame and line events; long packets start a word counter.
• Compute CRC-16 over the payload and compare with the footer. Flag errors on the output.
• Emit an AXI4-Stream: data on TDATA, start of frame on TUSER, end of line (end of chirp) on TLAST, virtual channel on TDEST.

5. Clock crossing and DMA

The receiver runs on the recovered 75 MHz byte clock, which only exists while the sensor is running. An asynchronous FIFO moves data to the system AXI clock (for example 150 MHz) before anything else. Then a DMA engine writes it to DDR through an HP port:

• AXI DMA (S2MM) treats the stream as packets. Simple, good when software walks chirps itself.
• VDMA treats the stream as a 2D frame (lines × bytes per line) with a stride and multiple frame buffers. A radar frame maps cleanly: lines = chirps, width = bytes per chirp. Frame-end interrupts tell the A9 a frame is ready.

Bandwidth is not tight. One AWR2243 peaks at 300 MB/s; two peak at 600 MB/s. A 64-bit HP port at 150 MHz moves about 1.2 GB/s. DDR3 at 1,066 MT/s gives about 2.1 GB/s peak on a 16-bit bus and 4.3 GB/s on 32-bit, roughly 60–70% of that in practice. The pressure comes from the PS and PL reading the same DDR for FFTs while new frames land. Ping-pong frame buffers and a few KB of BRAM FIFO per link (one chirp's worth) keep a DMA stall from dropping data. A full frame from both chips (2 × 512 KB in the example on the AWR2243 page) is small next to 128 MB of DDR.

Three ways to build it

Constraints sketch

## One 4-lane link, 600 Mb/s, bank 35 at VCCO = 1.2 V (pins are placeholders)
create_clock -name csi_bitclk -period 3.333 [get_ports csi_clk_p]

set_property IOSTANDARD LVDS_25  [get_ports {csi_clk_p csi_d_p[*]}]
set_property DIFF_TERM  FALSE    [get_ports {csi_clk_p csi_d_p[*]}]
set_property IOSTANDARD HSUL_12  [get_ports {csi_lp_dp[*] csi_lp_dn[*]}]

## BUFR is CLKDIV for the ISERDES; Vivado derives the /4 clock.
## Data capture is source-synchronous on BUFIO; per-lane alignment
## comes from IDELAY taps and sync search, not from input-delay constraints.
set_property IODELAY_GROUP csi_grp [get_cells -hier *idelay*]
set_property IODELAY_GROUP csi_grp [get_cells -hier *idelayctrl*]
set_clock_groups -asynchronous -group csi_bitclk -group clk_fpga_0

Failure modes from bring-up

Questions to expect