Page 4 · Choosing a PHY

D-PHY vs C-PHY

CSI-2 packets are the same on either PHY. What changes is how bits become voltages: D-PHY sends one bit per unit interval on differential pairs with a forwarded clock; C-PHY sends 3-phase symbols on wire trios with the clock embedded in the symbol transitions.

C-PHY in one picture

In every symbol one wire is high, one is low and one is at mid level, which gives six wire states (±x, ±y, ±z). The state must change every symbol, either by rotating which wire is high or by flipping polarity, so the receiver recovers the clock from the transitions themselves.

A C-PHY trio is three wires, A, B and C. At any instant one wire is driven high, one low, and one to the midpoint, so the sum of the three is constant and the common mode stays fixed. That gives six possible wire states. Each wire is terminated with 50 Ω to a common node, so any two wires see 100 Ω between them.

The receiver has three differential comparators: A−B, B−C and C−A. Because one wire is always at mid level, each comparator sees either a strong difference (high vs low, about two units) or a weak one (high or low vs mid, one unit). It never sees zero, so every comparator always resolves to 1 or 0.

How bits become symbols

The state must change on every symbol. From any state there are exactly five legal next states: four rotations (shift which wire is high, clockwise or counter-clockwise, with either polarity) and one flip (same wires, polarity inverted).
Five choices per symbol is log₂5 ≈ 2.32 bits. The mapper takes a 16-bit word and encodes it as 7 symbols, because 5⁷ = 78,125 ≥ 2¹⁶ = 65,536. Effective rate is 16/7 ≈ 2.28 bits per symbol.
Since every symbol has a transition, the receiver recovers the clock by ORing the three comparator outputs. No clock lane is needed. The comparators do not switch at exactly the same instant, so the receiver masks the jitter between the first and last comparator edge. That "encoding jitter" is C-PHY's main signal-integrity cost.

Side by side

	D-PHY	C-PHY
Wires per data channel	2 (lane) + a shared 2-wire clock lane	3 (trio), no clock lane
Clocking	Forwarded DDR clock, source-synchronous	Embedded; clock recovered from symbol transitions
Coding	None (1 bit per UI, NRZ)	3-phase, 16 bits → 7 symbols, 2.28 bits/symbol
Rate per channel	2.5 Gb/s (v1.2), 4.5 Gb/s (v2.x)	2.5 Gsym/s = 5.7 Gb/s (v1.0); about 6 Gsym/s ≈ 13.7 Gb/s (v2.0)
Typical config	Clock + 4 lanes = 10 wires	3 trios = 9 wires
Skew budget	Every data pair matched to the clock pair	Only the three wires inside a trio matched; trios independent
HS termination	100 Ω differential, switched	50 Ω per wire to a common node, switched
LP signaling	1.2 V LP states on Dp/Dn	Same 1.2 V LP states, reused
Receiver complexity	Low; capture with the forwarded clock	Higher; clock recovery, symbol decoder, demapper
Where it's used	Most industrial, automotive, embedded and FPGA designs; radar front ends	High-resolution phone cameras, some displays
FPGA support	Hard PHY on newer families; resistor-network workaround on older ones	Needs a native PHY or a bridge chip; no practical resistor-network solution

Pin budget

Same connector budget, different outcome. D-PHY spends two wires on a forwarded clock and gets one bit per UI per pair. C-PHY embeds the clock and gets about 2.28 bits per symbol per trio.

The headline advantage of C-PHY is bandwidth per pin. At the same symbol rate as a D-PHY bit rate, three trios carry about 70% more than four D-PHY lanes on one fewer wire. Phone SoCs often use combo PHYs: the same 10 or so pads can be configured as a 4-lane D-PHY or a 3-trio C-PHY, which lets one camera port accept either kind of sensor.

Choosing between them

Choose D-PHY when the bandwidth fits in four lanes, the receiver is an FPGA or a mid-range SoC, the sensor family only offers D-PHY (most automotive and radar parts), or you want simple bring-up with a scope and a forwarded clock you can trigger on.
Choose C-PHY when a 50–200 MP sensor has to run at video rates on a flex cable with a fixed pin count, and the SoC has a native C-PHY receiver.
Neither when the link leaves the PCB. Use a SerDes (GMSL, FPD-Link, A-PHY) that carries CSI-2 over coax or STP and regenerates it at the far end.

Questions to expect

How does C-PHY get more than 2 bits per symbol?

Six wire states, and the rule that the state must change every symbol leaves five choices per symbol. log₂5 is 2.32 bits. The 16-bit-to-7-symbol mapper captures 2.28 of that because 5⁷ just exceeds 2¹⁶.

Why doesn't C-PHY need a clock lane?

Because the state always changes, every symbol boundary has at least one comparator transition. The receiver ORs the three comparator outputs to generate a symbol clock, then masks the spread between comparator edges.

Which is better for EMI?

Both keep a constant common mode in HS. D-PHY pairs are classic differential and couple well to tightly matched routing. C-PHY trios don't form a clean differential pair, so their near-field is less symmetric, but they also have no continuously running clock lane radiating a single tone. In practice both rely on the scrambling option and good layout. On a radar board the bigger concern is keeping any of this away from the RF and LO routing.