Interface primer

Signaling Standards Primer

LVCMOS, LVDS, HDMI, DisplayPort, eDP and DSI from the electrical layer up: how each puts a bit on a wire, the pins between the application processor and the device, and what the board has to get right.

CoversLVCMOS, LVDS / OpenLDI, HDMI (TMDS and FRL), DisplayPort, eDP, MIPI DSI

Common threadHow a bit becomes a voltage or current on a wire, and what the board must do to keep it clean

Each pageHow it works, electrical levels, pin-level block diagram, SI / PI / EMC design table

Four ways to put a bit on a wire

Every interface here is a choice among a few electrical ideas. Knowing which one an interface uses tells you most of its design rules before you open the spec.

Scheme	How the bit is made	Used by	What it costs you
Single-ended voltage mode	A push-pull CMOS stage connects the wire to VDD or ground. The bit is the absolute voltage against the receiver's ground.	LVCMOS (GPIO, parallel RGB, DVP cameras, SPI, I²S)	Every edge moves C·V² of charge through the supply and ground. Ground differences and noise add directly to the signal.
Differential current mode	A constant current is steered one way or the other through a termination resistor. The bit is the sign of the voltage across it.	LVDS, sub-LVDS, OpenLDI, FPD-Link	Needs two wires per signal and a termination; supply current is nearly constant.
Open-drain differential into pull-ups	The transmitter sinks a current from one of two 50 Ω pull-ups at the receiver.	HDMI TMDS	The receiver sets the voltage levels; a 3.3 V termination must exist at the far end.
AC-coupled CML with a SerDes	A current-mode-logic driver with on-die 50 Ω terminations, series capacitors, an embedded clock and equalization.	DisplayPort, eDP, HDMI 2.1 FRL, PCIe, USB	Data must be DC-balanced (coding or scrambling); link training; loss budgets in dB.

Single-ended wire voltage ranges, drawn to one scale. Differential swing is twice the per-wire swing. DisplayPort's range depends on the receiver's bias because the link is AC-coupled; the bar shows a typical 600 mV swing.

Comparison

	LVCMOS (parallel RGB)	LVDS (OpenLDI)	HDMI 1.4 / 2.0 / 2.1	DisplayPort / eDP	MIPI DSI
Signals	~28 single-ended	4–5 pairs (single link)	4 pairs + DDC, HPD, CEC, 5 V	1–4 pairs + AUX pair + HPD	clock + 1–4 pairs
Clock	forwarded (PCLK)	forwarded pair	forwarded clock pair (TMDS); embedded in FRL	embedded	forwarded DDR clock
Rate per lane	≤ ~100 MHz per pin, practical	~0.6–1 Gb/s	3.4 / 6 / 12 Gb/s	1.62–8.1 Gb/s (DP1.4); up to 20 Gb/s (DP2.x)	~1.5–2.5 Gb/s (D-PHY), more on C-PHY
Coupling	DC	DC	DC (TMDS), AC on FRL sinks	AC	DC
Reach	centimeters	tens of cm (flex/cable)	meters (cable)	meters (DP) / internal (eDP)	centimeters
Typical use	small TFT panels, DVP cameras, FPGAs	industrial and automotive panels	external monitors and TVs	monitors (DP), laptop and tablet panels (eDP)	phone and small embedded panels

Design considerations that apply to all of them

When is a trace a transmission line? When its one-way delay exceeds about one sixth of the signal rise time. FR-4 stripline is roughly 6–7 ps/mm, so a 1 ns edge needs termination beyond about 25 mm, and a 100 ps edge beyond about 2.5 mm. Above that length, impedance control and termination are not optional.
Return current follows the signal. At high frequency the return flows in the reference plane directly under the trace, because that is the path of least inductance. A split, a slot or a layer change without a nearby stitching via forces a detour that radiates and causes crosstalk.
Differential pairs. Matched length inside the pair (skew converts differential signal into common mode, which radiates), constant spacing, constant reference plane, symmetrical vias.
Power integrity. Supply noise on the I/O rail moves single-ended thresholds directly; on PLL and SerDes rails it becomes jitter. Decouple by frequency band, and isolate PLL supplies.
ESD at connectors. Protection capacitance loads the line. For multi-Gb/s lanes, use parts under ~0.5 pF with flow-through layout.

The pages

LVCMOSPush-pull drivers, JESD8 thresholds, parallel RGB and DVP pins, reflections and series termination, SSO ground bounce. LVDSCurrent steering, TIA/EIA-644 levels, OpenLDI 7:1 pin-out, single and dual link, pair routing and common-mode noise. HDMITMDS open-drain drivers and 3.3 V terminations, 8b/10b TMDS coding, HDMI 2.1 FRL, connector pins, DDC/HPD/CEC, ESD and level shifting. DP, eDP & DSIAC-coupled main link, voltage swing and pre-emphasis, link training over AUX, eDP panel pins, and MIPI DSI.

The one-minute answer

If asked "how do these differ?"

LVCMOS is single-ended push-pull: simple, but every edge dumps C·V² into the rails and it only works over short traces with series termination. LVDS steers a constant 3.5 mA through a 100 Ω termination for ±350 mV around 1.2 V: quiet, low power, fine to a gigabit per pair. HDMI's TMDS is open-drain current into 50 Ω pull-ups to 3.3 V at the sink, with 8b/10b transition-minimized coding and a forwarded clock; HDMI 2.1 drops the clock for 4 lanes of 12 Gb/s FRL. DisplayPort is AC-coupled CML with an embedded clock, adjustable swing and pre-emphasis negotiated in link training over the AUX channel; eDP is its internal-panel version. DSI is MIPI D-PHY carrying display packets.