Page 3 · Bits to voltages
Modulation
NRZ, NRZI, Manchester, MLT-3, PAM3 and PAM4: what each looks like on the wire, how many bits it carries per symbol, and what it costs in eye height.
NRZ
Non-return-to-zero: one bit per symbol, held for the whole unit interval (UI). It is the most efficient use of the eye: the full swing separates one decision. Its fastest pattern, 1010…, has a fundamental at half the bit rate, the Nyquist frequency. NRZ has no built-in transitions or DC balance; a block code or scrambler supplies them.
NRZI
Non-return-to-zero inverted: a 1 is a transition, a 0 is no transition. The receiver only needs to detect change, so polarity does not matter (a swapped pair still works). Long runs of 1s become a square wave; long runs of 0s are still flat, which is why NRZI is paired with 4b/5b (FDDI, 100BASE-FX) or bit stuffing (USB 2.0).
Manchester
Every bit has a transition in its middle: in IEEE 802.3, a 1 rises and a 0 falls (G. E. Thomas's original convention is the reverse). That guarantees a clock edge every bit and a perfect DC balance, at the cost of twice the bandwidth: a run of identical bits toggles at the full bit rate. Fine at 10 Mb/s (10BASE-T, MIL-STD-1553, DisplayPort AUX at 1 Mb/s), wasteful at Gb/s.
MLT-3
Multi-level transmit, three levels: each 1 steps to the next state in the cycle 0, +, 0, −; a 0 holds. Four 1s make one full cycle, so even the fastest pattern has a fundamental at a quarter of the symbol rate. 100BASE-TX sends 125 MBd (after 4b/5b) with most energy below about 31 MHz, which kept it inside Cat-5 cable bandwidth and FCC emission limits. The receiver still makes two-level decisions about "change or no change", so MLT-3 is a spectral shaping trick rather than a way to send more bits per symbol.
PAM-M: more bits per symbol
Pulse-amplitude modulation with M levels carries log₂M bits per symbol. The symbol rate, and so the Nyquist frequency, drops by that factor for the same bit rate. The price is that M levels in the same swing leave M − 1 eyes, each 1/(M − 1) as tall.
| NRZ (PAM2) | PAM3 | PAM4 | |
|---|---|---|---|
| Levels | 2 | 3 | 4 |
| Bits per symbol | 1 | log₂3 = 1.58 (usually 3 bits in 2 symbols = 1.5) | 2 |
| Nyquist at 12 Gb/s | 6 GHz | 4 GHz | 3 GHz |
| Eye height | 1 | ½ | ⅓ |
| SNR penalty | 0 dB | 6.0 dB | 9.5 dB |
| Linearity | not needed | one middle level | three thresholds; level spacing (RLM) matters |
| Examples | most links | 100BASE-T1, 1000BASE-T1, USB4 v2, GDDR7 | GMSL3, PCIe 6, 200/400G Ethernet, GDDR6X |
When does PAM4 win?
PAM4 pays 9.5 dB in eye height and saves the channel loss between f_N and f_N/2. On a channel losing 21 dB at 3 GHz and 33 dB at 6 GHz, 12 Gb/s NRZ would face 12 dB more loss than 12 Gb/s PAM4 (see the GMSL Primer), so PAM4 comes out ahead by about 2–3 dB. On a short, low-loss channel the trade goes the other way, which is why NRZ survived up to 32 GT/s in PCIe 5.
Gray coding
PAM4 maps bit pairs to levels as 00, 01, 11, 10 from bottom to top, so neighboring levels differ in one bit. Noise almost always pushes a symbol to an adjacent level, so a symbol error usually costs one bit error, not two.
PAM3 mappings
Three levels hold 1.58 bits, but bits come in powers of two. Practical schemes map groups: 3 bits into 2 ternary symbols (9 states for 8 values) in 100BASE-T1's 3B2T, or 11 bits into 7 symbols in USB4 v2. The spare states can carry control codes.
C-PHY: modulation across wires
MIPI C-PHY uses three wires per lane, each at one of three levels, with a different wire at each level in every symbol. Each symbol must change state, so the clock is embedded in every symbol boundary. There are six wire states and each symbol moves to one of the other five, so each symbol carries log₂5 ≈ 2.32 bits, and 16 bits are packed into 7 symbols, 2.28 bits per symbol.