Page 2 · Why codes exist

Foundations

The three physical problems every line code solves: AC coupling, clock recovery and alignment. Each one gives a number a code has to meet.

1. DC balance and baseline wander

Most links pass through a series capacitor or a transformer. Both block DC: a capacitor because its impedance 1/(2πfC) is infinite at f = 0, a transformer because a constant current produces no changing flux. Together with the termination they form a high-pass filter with time constant τ.

Computed: NRZ through a first-order high-pass with a time constant of 18 bits (exaggerated so it is visible). During a long run the received level droops toward the threshold, and the bits after the run start offset. Real links use time constants of thousands of bits, and the line code bounds how unbalanced the data can get.

droop after N identical bits = 1 − e^(−N·T_b / τ) τ = C · (R_source + R_load)100 nF between two 50 Ω terminations gives τ = 10 µs. At 6 Gb/s that is 60,000 bits; a run of 600 identical bits droops by 1%. The real problem is not one run but a sustained imbalance: if the stream averages 55% ones for thousands of bits, the baseline settles 10% of the swing off center, and every decision loses that much margin.

The measure is running digital sum (RDS): add +1 for each one and −1 for each zero. A DC-balanced code keeps RDS inside fixed bounds forever. 8b/10b bounds it to a few bits; Manchester returns to zero every bit; a scrambler only makes large excursions unlikely.

2. Run length and clock recovery

A serial receiver has no clock wire. Its clock-and-data-recovery (CDR) loop learns the phase from data edges.

A bang-bang (Alexander) CDR samples each bit in its center and at its edges. On a transition, the edge sample shows whether the clock is early or late, and the loop nudges the phase. With no transitions it gets no information and coasts.

Between edges the CDR coasts at its own frequency, which differs from the transmitter's by the two reference oscillators' error. During a run with no transitions, the sampling point drifts.

phase drift = Δf / f × run length (in UI)PCIe allows each side ±300 ppm, so up to 600 ppm between them. Over 5 bits (8b/10b's maximum run) that is 0.003 UI. Over 66 bits (64b/66b's worst case) it is 0.04 UI. Over 10,000 bits of unscrambled zeros it would be 6 UI: the receiver would lose count. Spread-spectrum clocking (up to 5,000 ppm of slow modulation) makes the loop work harder and tightens the limit further.

Run length also matters for the CDR loop's stability: the phase detector's gain depends on transition density. A code with a guaranteed minimum density gives a predictable loop bandwidth and jitter tolerance.

3. Scrambling

A scrambler XORs the data with a pseudo-random sequence from a linear feedback shift register (LFSR). The output looks random: half ones on average, runs that are exponentially unlikely to be long (probability ~2⁻ᴺ for a run of N), and a flat, noise-like spectrum. It adds no overhead, but it guarantees nothing; it only makes bad patterns improbable.

Type	How it works	Pros	Cons	Used in
Additive (frame-synchronous)	XOR with an LFSR that runs independently and is reset at known points	No error multiplication	Both ends must reset the LFSR together (needs framing)	PCIe 1–5, SATA, DisplayPort, USB 3
Multiplicative (self-synchronous)	Output feeds back into the LFSR; descrambler uses received bits	Locks by itself after one register length	One line error causes (1 + number of taps) output errors	64b/66b (10GBASE-R), SONET payload, some modems

Each output bit is the input XORed with two earlier output bits. The descrambler runs the same taps on the received stream, so it locks by itself after 58 bits with no shared seed. The cost is error multiplication: one line error corrupts three output bits (the bit itself and the two places it is used as a tap).

Scrambling has a second benefit: it spreads repetitive data (an all-black screen, an idle link) across the spectrum instead of putting it into spectral lines, which lowers peak EMI. That is why PCIe Gen 1 and 2 scrambled even under 8b/10b, and why HDMI 2.0 added scrambling.

4. Bit stuffing, the cheap alternative

CAN and USB 2.0 (with NRZI) insert a complementary bit after a fixed number of identical bits: after 5 in CAN, after six 1s in USB 2.0. The receiver removes it. Overhead depends on the data (worst case ~20% in CAN), which makes frame length variable. It bounds run length but does not balance DC; CAN and USB 2.0 are DC-coupled.

Putting it together

Method	DC balance	Run length	Alignment	Overhead
Manchester	perfect (every bit)	≤ 2 half-bits	needs a preamble	100% (2× bandwidth)
4b/5b + NRZI	no	≤ 3 zeros	J/K symbols	25%
8b/10b	bounded RDS	≤ 5	K28.5 comma	25%
64b/66b + scrambler	statistical	≤ 66 (header edge), usually short	sync header	3.1%
128b/130b + scrambler	statistical	bounded by headers, usually short	sync header + ordered sets	1.6%
Bit stuffing	no	≤ 5 or 6	start of frame	data-dependent
Plain scrambling	statistical	unbounded, rare	needs framing	0%