Page 4 · Bits to symbols

Block Codes

How 4b/5b, 8b/10b, 64b/66b, 128b/130b and 128b/132b turn raw bits into a stream with transitions, balance and alignment, and what each costs in overhead.

4b/5b

Each 4-bit nibble maps to one of 32 five-bit codes. Sixteen are chosen so that no code has more than one leading zero or more than two trailing zeros, so no more than three zeros ever appear in a row. Sent with NRZI (where a 1 is a transition), that guarantees an edge at least every 4 bits. Some of the spare codes are control symbols (J/K start delimiter, T/R end, idle). It does not balance DC, which is acceptable on fiber (FDDI, 100BASE-FX) and on 100BASE-TX, where a scrambler and MLT-3 follow.

8b/10b

1. Split. Each byte is split into its low 5 bits (EDCBA) and high 3 bits (HGF), written Dx.y: D21.5 is the byte with x = 21, y = 5.
2. Encode. 5 bits → 6 bits and 3 bits → 4 bits from fixed tables. Every code word has disparity 0 (equal 1s and 0s) or ±2.
3. Balance. For unbalanced code words both polarities exist. The running disparity (RD) picks the one that pulls the line back toward zero, then flips. RD only ever takes the values −1 and +1.
4. Guarantees. No more than 5 identical bits in a row, at least 3 transitions per 10-bit symbol, and DC balance bounded at all times.
5. Control symbols. Twelve K-codes exist outside the data set. K28.5 contains the comma pattern 0011111 or 1100000, which cannot appear in data even across symbol boundaries, so the receiver aligns on it.
6. Error detection for free. A bit error often produces an invalid code word or a disparity violation, which the receiver flags immediately.

64b/66b

Instead of mapping through tables, 64b/66b prefixes each 64-bit block with a 2-bit sync header and scrambles the payload.

• Header. 01 for a data block, 10 for a control block. 00 and 11 are invalid. Because the header always contains a transition, there is at least one edge every 66 bits, and the receiver finds block boundaries by searching for the bit position where the header is always 01 or 10.
• Payload. Self-synchronizing scrambler with polynomial 1 + x³⁹ + x⁵⁸. Runs and imbalance are statistically bounded, not guaranteed. The scrambler is long enough that a malicious pattern would have to match 58 bits of scrambler state.
• Control blocks. An 8-bit type field says how the remaining 56 bits are split between control characters and data (for example, start or end of an Ethernet frame inside the block).
• Error multiplication. One bit error becomes three after descrambling. Ethernet's CRC-32 is chosen so that this still gets detected.

128b/130b

PCIe 3.0, 4.0 and 5.0 use the same idea with a longer block: a 2-bit header (01 data, 10 ordered set) and 128 bits of payload, scrambled with an additive LFSR that both ends reset at defined points. Ordered sets carry training, skip (clock compensation) and electrical-idle signals. The longer block halves the header overhead again.

128b/132b

USB 3.1 Gen 2 (10 Gb/s) and DisplayPort 2.x UHBR rates use a 4-bit header with 128 scrambled bits. The four header bits encode two values with enough redundancy that a single bit error in the header can be corrected, which matters because a corrupted header loses a whole block.

Other codes you will meet

Overhead summary