Interface primer
Line Coding Primer
How serial links turn bits into symbols and symbols into voltages: modulation schemes, block codes and scramblers, built up from the physics that makes them necessary.
Two separate jobs
A serial link has to solve two problems that are easy to confuse. Line coding rearranges the bits so the stream has properties the electronics need: enough transitions for the receiver to recover the clock, an average of zero so it survives AC coupling, and marker patterns so the receiver can find word boundaries. Modulation decides how each symbol becomes a voltage: two levels, three, four, or a transition in the middle of the bit.
The two combine. 100BASE-TX is 4b/5b coding sent with MLT-3 modulation. PCIe 3 is 128b/130b with scrambling sent as NRZ. PCIe 6 is PAM4 with forward error correction and no block code at all.
The four constraints every code answers
| Constraint | Physics | Fixed by |
|---|---|---|
| DC balance | AC-coupling capacitors and transformers are high-pass filters; a stream with a non-zero average drifts the baseline. | 8b/10b running disparity, Manchester, scrambling (statistically), TMDS |
| Transition density | The CDR only learns the phase from edges. Long runs let the clock drift off the bit center. | Bounded run length (8b/10b ≤ 5), sync headers (64b/66b), scrambling, bit stuffing (CAN) |
| Alignment | The receiver sees a bit stream and must find where symbols and blocks begin. | Comma characters (K28.5), sync headers, start bits (UART) |
| Bandwidth | Channel loss grows with frequency; the Nyquist frequency is half the symbol rate. | Multi-level modulation (PAM3/4) or energy-concentrating codes (MLT-3) |
Which interface uses what, and why
| Interface | Modulation | Code | Efficiency | Why this choice |
|---|---|---|---|---|
| UART | NRZ | start + stop bits per byte | 80% (8N1) | No clock: resync on every start edge; trivial to implement |
| CAN / CAN FD | NRZ | bit stuffing after 5 equal bits | variable, ~85–95% | Bounded run length for resync on a multi-drop bus |
| I²C, SPI, MIPI D-PHY | NRZ | none | 100% | Clock is forwarded on its own wire, so no CDR is needed |
| 10BASE-T Ethernet, DP AUX | Manchester | built in | 50% | Self-clocking and DC-free; cheap at low rates where bandwidth is cheap |
| 100BASE-TX Ethernet | MLT-3 | 4b/5b + scrambler | 80% | 125 MBd but energy mostly below ~31 MHz to fit Cat-5 and EMC limits |
| 100BASE-T1 (automotive) | PAM3 | 4B3B, then 3B2T | ~2 bits per 1.33 symbols | 66.67 MBd on one unshielded pair; lower spectrum for EMC |
| 1000BASE-T1 (automotive) | PAM3 | RS-FEC framing | — | 750 MBd on one pair |
| Gigabit Ethernet (1000BASE-X), SATA, PCIe 1/2, USB 3.0 Gen 1, DP 1.x, JESD204B | NRZ | 8b/10b | 80% | Strict DC balance, run length ≤ 5, commas; simple at a few Gb/s |
| HDMI TMDS | NRZ | TMDS 8→10 (transition-minimized, DC-balanced) | 80% | Fewer edges for lower EMI on the cable, plus DC balance |
| HDMI 2.1 FRL | NRZ | 16b/18b + scrambling | 89% | Higher efficiency at 12 Gb/s per lane |
| 10G/25G/100G Ethernet, JESD204C | NRZ | 64b/66b + self-sync scrambler | 97% | Low overhead; scrambler gives balance statistically |
| PCIe 3, 4, 5 | NRZ | 128b/130b + scrambler | 98.5% | Frees bandwidth that 8b/10b wasted; Gen 3 went to 8 GT/s instead of 10 |
| USB 3.1 Gen 2+, DP 2.x (UHBR) | NRZ | 128b/132b + scrambler | 97% | 4-bit header with redundancy tolerates a header bit error |
| MIPI C-PHY | 3-phase, 3 wires | 16 bits → 7 symbols | 2.28 bits/symbol | Embedded clock in every symbol transition |
| GMSL3, PCIe 6, 400G Ethernet, GDDR6X | PAM4 | FEC (PCIe 6: FLIT-based) | — | Halve Nyquist frequency at 50–100+ Gb/s; FEC recovers the SNR lost |
| USB4 v2, GDDR7 | PAM3 | multi-bit-to-ternary mapping | 1.5 bits/symbol | Middle ground: 6 dB penalty instead of 9.5 dB |
Efficiency is payload bits divided by line bits. For multi-level schemes it is clearer to compare bits per symbol, because the symbol rate sets the bandwidth.
The pages
The one-minute answer
Raw data can be all ones or all zeros for a long time. That breaks two things: AC coupling, which needs an average of zero or the baseline drifts, and clock recovery, which needs edges to track phase. Codes like 8b/10b fix both deterministically for 20% overhead: run length at most 5, running disparity at most ±1, plus comma characters for alignment. Newer links use 64b/66b or 128b/130b: a 2-bit header that always has a transition, and a scrambler that makes the payload statistically random, for 2–3% overhead. Modulation is separate: NRZ sends one bit per symbol; PAM4 sends two to halve the Nyquist frequency, at a 9.5 dB eye penalty that usually needs FEC.