Page 4 · Putting it to work

Cameras and Displays

The full path from a photon at the sensor to a frame in SoC memory, the display direction, bandwidth sizing, and how to design and debug the link.

Camera to processor, end to end

  1. Sensor configured. At boot the SoC writes the deserializer over local I²C, brings up each link, and then writes each sensor's registers through the tunnel: mode, exposure, lane count, data type.
  2. Exposure. A frame-sync pulse from the ECU starts exposure on every camera (below). The sensor reads out its rows as CSI-2 long packets, framed by FS/FE and LS/LE short packets.
  3. Serialize. The serializer's CSI-2 receiver takes the 4-lane D-PHY bursts, buffers them, wraps them in GMSL packets with CRC, scrambles and drives 6 Gb/s onto the coax.
  4. Cross the cable. About 4 ns per meter of flight, 20 dB of loss at Nyquist, plus power going the other way on the same conductor.
  5. Deserialize. CTLE and DFE flatten the channel; CDR recovers the clock; the CRC is checked; the VC is remapped; lines from up to four cameras are interleaved onto a CSI-2 output.
  6. Into the SoC. The SoC's CSI-2 receiver demultiplexes by VC and DMAs each camera into its own buffer. The ISP debayers and the frames go to perception. Added link latency is microseconds; the frame time is 16–33 ms.

Bandwidth math

rate = width × height × bits/pixel × fps × (1 + blanking overhead)Payload must fit under the link's usable rate, which is below the line rate after coding and packet overhead.
CameraRaw pixel rateWith ~10% overheadLink
1920×1080 RAW12, 30 fps0.75 Gb/s~0.8 Gb/sGMSL2 3 Gb/s
1920×1080 RAW12, 60 fps1.49 Gb/s~1.6 Gb/sGMSL2 3 Gb/s
3840×2160 (8 MP) RAW12, 30 fps2.99 Gb/s~3.3 Gb/sGMSL2 6 Gb/s
3840×2160 RAW12, 60 fps5.97 Gb/s~6.6 Gb/sGMSL3 12 Gb/s
Radar raw ADC, CSI-2 4 × 600 Mb/s (AWR2243-class)2.4 Gb/s~2.6 Gb/sGMSL2 6 Gb/s (3 Gb/s too tight)

The last row connects to your radar board. The board kept DSP on the sensor because a 100 Mb/s automotive Ethernet link capped what could leave it. A GMSL-class link is the other architecture: ship raw ADC samples to a central processor and do the FFTs there. The trade is cable and central compute cost against sensor-side power, heat and silicon.

Frame synchronization

Deserializergenerates FSYNCSerializer 0GPIO outSensor 0FSYNC pinSerializer 1GPIO outSensor 1FSYNC pinSerializer 2GPIO outSensor 2FSYNC pinSerializer 3GPIO outSensor 3FSYNC pinSoCtimestampstrigger / PPSsame latencyto every camera
One frame-sync pulse leaves the deserializer as a reverse-channel GPIO packet and reaches every camera with the same, fixed latency. With the sensors already frequency-locked, all exposures start together, which stereo and multi-view fusion depend on.

Displays: the same link reversed

SoCDSI or DP/eDPSerializerin the ECUDeserializerin the displayTCON / paneloLDI, eDP, DSIpixels forwardtouch · statusTouch controllerI²C
For displays the serializer is in the ECU and the deserializer is in the panel. The fast direction now carries pixels to the display; the slow direction brings back touch coordinates and panel status.

Display links add things cameras do not need: HDCP encryption for protected content, Display Stream Compression on GMSL2 to fit 4K over one cable, and on GMSL3 daisy-chaining several displays from one serializer.

On a robot

Board design checklist

Debug order when a camera drops

  1. Power. Read the PoC voltage at the camera through the serializer ADC, or measure it. Low voltage under load means drop or a saturating inductor.
  2. Lock. No lock: check line-fault status (open/short), connector seating, rate settings on both ends.
  3. Margin. Lock but errors: read the eye monitor and EQ settings, run PRBS, then heat and cool the harness to find where margin collapses.
  4. Correlate. Errors only when motors run point to common-mode noise or shield bonding. Errors only when moving point to a cable or slip ring.
  5. Above the link. Link clean but no image: CSI-2 settings (lanes, data type, VC mapping) and sensor configuration.

Questions to practice

Why does GMSL3 use PAM4 instead of a faster NRZ?

NRZ at 12 Gb/s puts Nyquist at 6 GHz, where cable loss is roughly 10–15 dB worse than at 3 GHz. PAM4 at 6 GBd keeps Nyquist at 3 GHz and pays a 9.5 dB eye-height penalty instead, plus tighter linearity and more coding. On automotive coax the PAM4 trade wins, and it reuses the GMSL2 channel.

How can both directions run on one conductor at once?

The line is linear, so the two waves superpose. The reverse channel sits mostly far below the forward channel in frequency, and where they overlap each end subtracts a replica of its own transmitted signal. Reflections it cannot model become noise, which is why return loss matters.

What limits the PoC inductor design?

It must be high impedance from the reverse channel's lowest frequency (~2 MHz) to above the forward channel's top (~3.5 GHz). That needs both a large inductance and a high self-resonant frequency, which one part cannot do, so a chain of inductors and a ferrite is used. It must also not saturate at the camera's DC current.

Why is the link AC-coupled?

To block the DC ground offset between camera and ECU, and to let DC power share the wire. AC coupling needs DC-balanced, scrambled data so the baseline does not wander and the CDR sees transitions.

How do you synchronize four cameras?

Lock their frequencies (reference over reverse, sensor clock from the serializer), then align their exposures with a frame-sync GPIO sent from the deserializer to all serializers with fixed latency. Timestamp at the deserializer or SoC.

A camera loses link only when the arm moves. What do you check?

Error counters and EQ settings during motion, cable flex damage and connector retention, slip-ring return loss, shield bonding, and whether the PoC voltage dips when motors draw current.

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