Page 3 · Packets and control

GMSL Link Layer

How video, control, GPIO and status share one bit stream in each direction, and how the far end rebuilds CSI-2.

The physical layer delivers a clean bit stream. The link layer decides what goes in it: video packets, control traffic, GPIO events and status, all multiplexed on one wire in each direction.

The data pipeline

The serializer takes CSI-2 apart into its packets, wraps them in GMSL packets, interleaves them with control traffic and scrambles the result. The deserializer runs the same steps backwards and can merge streams from several links before sending CSI-2 to the SoC.

Packets, not a raw bit pipe

GMSL2 and GMSL3 are packet links. Each packet has a header naming its stream and type, a payload, and a CRC. That lets one wire carry several independent streams with different priorities.

The forward channel is a stream of small packets. Video dominates, but control replies, GPIO edges and status packets slot in between, so a register read-back never waits for a frame to finish.

Stream	Direction	What it carries
Video	forward	CSI-2 long packets (lines of RAW or YUV) and short packets (frame and line start/end), or display pixels
I²C / UART	both	Register writes go out on the reverse channel; ACKs and read data come back forward. MAX96793 class parts tunnel two I²C/UART channels at up to 1 Mb/s I²C.
SPI	both	A tunneled SPI port (up to 25 MHz on MAX96793) for faster configuration or small sensor payloads
GPIO	both	Pin changes sent as packets: frame sync, sensor reset, interrupts, power-good
Info / status	both	Link state, error counters, ADC readings (voltage, temperature), line-fault results
Ethernet (GMSL2+)	both	Tunneled Ethernet for devices that need it

Tunnel mode and pixel mode

A GMSL2 serializer can treat CSI-2 in two ways.

Tunnel mode carries the CSI-2 packets through unchanged. The deserializer re-emits them byte for byte. Simple and transparent; the CSI-2 rate and format at the output match the input.
Pixel mode unpacks CSI-2 into pixels and repacks them at the far end. That lets the deserializer change lane count, data rate, virtual channel and data type, and merge streams from several cameras into one CSI-2 port.

Virtual channels and aggregation

CSI-2 headers carry a virtual channel (VC) number. A quad deserializer such as the MAX96712 receives four cameras that all transmit on VC 0, remaps them to VC 0, 1, 2 and 3, and interleaves them line by line onto one or two CSI-2 output ports. The SoC's CSI-2 receiver sorts the lines back into four frame buffers by VC.

Output ≥ Σ camera rates 4 × 1.5 Gb/s = 6 Gb/s ≤ 4 lanes × 2.5 Gb/s = 10 Gb/sThe output port has to carry the sum of the inputs plus packet overhead, and its buffering has to absorb lines arriving at the same moment from cameras that are not perfectly synchronized.

Control tunneling

The SoC talks I²C to the deserializer as if the sensors were local. The deserializer packs each transaction into reverse-channel packets; the remote serializer replays it as a real I²C master and returns ACKs and read data. Identical cameras share one address, so each serializer translates an alias address to the real one.

I²C is a slow open-drain bus that expects a reply within a clock period. Over a link it cannot be truly transparent, so the deserializer stretches the clock (holds SCL low) while the transaction travels to the camera and the ACK comes back. Round-trip latency is microseconds, small next to an I²C bit at 400 kHz (2.5 µs), but it adds up for long register scripts.

Clocking

Three clocks have to be consistent: the link clock, the sensor's pixel clock, and the SoC's frame timing.

Link clock. The forward rate is fixed (3, 6 or 12 Gb/s), set by the serializer's PLL. The deserializer locks to it with its CDR.
Reference over reverse. Newer serializers (MAX96793, for example) run crystal-free: the deserializer's reference frequency is carried on the reverse channel and the serializer's PLL locks to it. One crystal on the ECU sets the frequency of every camera.
Sensor clock. The serializer can output a reference clock for the image sensor, so the sensor is frequency-locked to the ECU too. Locked frequency is not the same as aligned exposure; that needs frame sync (next page).

Errors and diagnostics

CSI-2 already has header ECC and payload CRC, but those cover only what the sensor produced. GMSL adds its own CRC per link packet, so the system can tell a cable fault from a sensor fault. Control packets are acknowledged and retransmitted when lost. Video is not retransmitted (there is no time), so a corrupted packet is counted and flagged instead.

Diagnostic	What it tells you
Link lock and lock-loss counter	Whether CDR and adaptation are stable, and how often they drop
CRC / decode error counters	BER in service; rising counts point to a degrading cable or connector
Eye-opening monitor	Margin after equalization, without a scope; trend it over temperature
Adaptive EQ settings read-back	Effective channel loss; a sudden change means the cable changed
Line-fault detection	Open, short to ground or short to battery on the coax
ADC and temperature	PoC voltage at the camera, supply rails, die temperature
PRBS generator and checker	Measure BER on a channel in the lab or end-of-line test

Recent parts (MAX96793 class) are developed for ASIL-B with ASIL-D decomposition, which is why the diagnostics list is long: each one closes a failure mode that safety analysis would otherwise flag.