Power integrity · from first principles
The question of mixing capacitor values, checked against the PI literature (sources in section 15) and built up one idea at a time: why decoupling exists, what a real capacitor is, where its inductance comes from, when identical parts beat mixed values and when they don't, how the board stackup joins in, and how to size a bank. The interactive version lives on a separate page, MLCC Decoupling Strategies.
A digital IC draws current in fast steps: a clock edge, a burst of logic, a SerDes lane waking up. The regulator is too far away and too slow to supply those edges, so the current comes from whatever sits between the regulator and the IC: capacitors, planes, the package. That network is the power delivery network (PDN).
The rail moves by the step current times the impedance the IC sees at that frequency:
So the whole job reduces to one number. If the rail can move by V × ripple and the largest step is ΔI, the PDN must stay under the target impedance across every frequency the load can excite:
Decoupling is not "add capacitors." It is "keep |Z| under a line from where the regulator stops helping to where the package takes over." Everything below is about how to do that.
Reactance is how strongly a part resists AC current. Capacitors and inductors resist in opposite directions as frequency changes.
| Element | Reactance | As frequency rises | On a log-log plot |
|---|---|---|---|
| Capacitor | XC = 1 / (2πfC) | Falls. More C lowers it at every frequency. | Line sloping down, −1 decade per decade |
| Inductor | XL = 2πfL | Rises. Less L lowers it at every frequency. | Line sloping up, +1 decade per decade |
| Resistor | R | Flat | Horizontal line |
They also differ in phase: a capacitor's voltage lags its current and an inductor's leads it. Alone, phase does not change the ripple; only |Z| does. Phase matters when the two are combined, because opposite reactances cancel. That cancellation drives sections 03 and 10.
A real MLCC on a board is capacitance C in series with resistance (ESR) and inductance L. Current has to pass through all three, so their reactances combine in series and subtract:
L here is the part's own ESL plus the mounting inductance of its pads, vias and plane connection. Section 07 builds that up. For now, take a 10 µF 0402 with 1 nH total and 4 mΩ ESR.
The V shape is the two straight lines meeting. Below the SRF the real curve rides XC; above it, XL. At the SRF the reactances cancel and only ESR is left, so the dip bottoms out at about 4 mΩ.
Because the reactances are in series, the larger one sets the impedance. The same part has two regimes with two different levers.
| Frequency | XC | XL | In charge | |Z| | Lever that helps |
|---|---|---|---|---|---|
| 100 kHz | 159 mΩ | 0.6 mΩ | Capacitance | ≈ 158 mΩ | More C (value or count) |
| 1.6 MHz | 10 mΩ | 10 mΩ | They cancel | ≈ 4 mΩ (ESR) | — |
| 100 MHz | 0.16 mΩ | 628 mΩ | Inductance | ≈ 628 mΩ | Less L (count, package, layout) |
From 1 to 100 MHz, XC gets 100× better and XL gets 100× worse. Lowering XC further does nothing once the current is stuck behind the inductance. Think of a large water tank feeding a long, thin pipe: a bigger tank does not increase flow when the pipe is the restriction.
Below SRF the value matters and inductance does not. Above SRF inductance matters and the value does not. The capacitance itself never changes with frequency (DC bias aside); only which term dominates changes.
On a log scale the two sides are mirror images around the SRF. What makes the inductive side look worse in practice is where the band sits: a 10 µF part resonates at 1.6 MHz but is asked to work from about 100 kHz (16× below) to 100 MHz (60× above). That is why the high end is usually the harder constraint.
A decoupling capacitor's job is a low-impedance path. The IC sees |Z|, not whether |Z| comes from C or from L. Above SRF |Z| ≈ 2πfL, which rises, but if L is small enough it can still be under target.
Most of an MLCC bank's useful band is above its SRF. A part fails as a decoupler when |Z| crosses the target, not when it becomes inductive. The one place phase does matter is when an inductive part sits in parallel with a capacitive one, which is section 10.
Inductance is magnetic flux per amp: L = Φ / I. Current flowing around a loop creates a field inside it. The more area the loop encloses, and the longer and narrower its conductors, the more flux each amp makes. Nothing in that definition involves capacitance; a copper loop of the same shape has the same inductance.
For a flat conductor carrying current over a return plane, which describes pads, traces and plane pairs alike:
Three ways to cut it: bring the return closer (smaller h), shorten the path (smaller ℓ), widen it (larger w). Two more: put opposing currents side by side so their fields cancel, and put paths in parallel so the current divides. Every layout rule in this primer is one of these five.
An MLCC is a stack of metal electrode sheets separated by ceramic. Alternate sheets connect to the left and right terminations. Current enters one end, spreads into the sheets, crosses the ceramic as displacement current, and leaves through the other end.
What sets capacitance: number of sheets, ceramic thickness between them, and dielectric constant. A 1 nF and a 10 µF 0402 differ only in these.
What sets ESL: the outer path, from one end of a 1.0 × 0.5 mm box to the other, at about the same height above the board. All sheets are in parallel between the same two terminations, so the outline of the loop does not change.
Across a 10,000× capacitance range in one package, ESL moves only by tens of percent.
| Package or style | Typical ESL | Why |
|---|---|---|
| 0603 | ~0.5–0.6 nH | Longer path between terminations |
| 0402 | ~0.35–0.45 nH | Shorter path |
| 0201 | ~0.2–0.3 nH | Shorter still, but less C available |
| Reverse geometry (0204) | ~0.1–0.2 nH | Terminations on the long sides: short, wide path |
| Interdigitated, multi-terminal | tens of pH | Alternating terminals put opposing currents side by side |
Figures are typical ranges for orientation, before mounting. Check the vendor's model for the exact part.
On a board the loop is: plane → via → pad → capacitor → pad → via → other plane. The part is one segment. The rest is layout, and it is usually the larger share.
Shrink the shaded loop and you shrink the inductance. Shorter vias, vias at the pad, and planes close to the surface all do that.
The pad is a segment of the loop. Using L ≈ μ₀·h·(ℓ/w) with 0.5 mm of current path, 0.5 mm wide:
Same pad, 5× the inductance, purely from plane depth. The pad's larger effect is where it forces the via to go. Via-in-pad sends current straight down at the termination, so almost no horizontal travel is left.
| Same 0402 part | Poor layout | Good layout |
|---|---|---|
| Pad to via | 1 mm trace each side | Via-in-pad, or vias at the pad edge |
| Vias per terminal | 1 | 2 or more, power and ground vias close together |
| Planes | Deep in the stack | Pair right under the cap's surface, thin dielectric |
| Placement | Far from the IC's power vias | At the IC's power and ground vias |
| Total mounted L | ~1.5–3 nH | ~0.4–0.6 nH |
Value sets capacitance. Package sets the floor on ESL. Layout decides most of the rest. A 3–4× change from layout alone is bigger than moving from 0603 to 0402. Measured mounted inductance of 2–3 nH is common even for 0402 parts when the planes sit deep in the stack.
N identical branches in parallel behave like one part with:
The whole curve drops by N at every frequency and keeps its shape. Every part turns inductive at the same frequency, so no branch is ever inductive while another is capacitive. There is nothing to resonate against.
1 µF 0402 parts, 1 nH each. Real boards fall short of a perfect N. Archambeault et al. found that caps clustered side by side add capacitance but lower the inductance the IC sees much less than L ÷ N, because the current still crowds into the IC's own vias. Spreading caps around the IC works better.
Now mix values in one package: 10 µF + 100 nF + 1 nF, all with about 1 nH. Above SRF all three share the same inductive line (section 04), so the smaller values add almost nothing there. Worse, between two resonances the larger part has already turned inductive while the smaller one is still capacitive.
An inductor in parallel with a capacitor is a tank circuit. Its impedance peaks where a series RLC would dip.
The peak sits where the loop reactances cancel, so current circulates between the two parts instead of being supplied by them:
The peak scales with 1/ESR. Better, lower-ESR parts make it taller and sharper.
The mixed bank wins briefly around 1–2 MHz, where its 10 µF part resonates. From about 5 to 100 MHz it is far worse: about 0.21 Ω at 11 MHz against about 6 mΩ for the identical bank.
Same value, many parts: C up, L down, no peaks between the parts. Low-ESR values decades apart, same package: no extra high-frequency coverage, plus tank peaks between resonances. The old "one value per decade" rule dates from leaded parts, where a smaller value also meant a smaller, lower-inductance body.
The problem is Q, not mixing as such. The peak height scales with 1/ESR. Novak et al. showed that banks of different values give a flat impedance when each bank's ESR matches its characteristic resistance √(L/C), using controlled-ESR parts. Bogatin, Smith and Sandler likewise say values or controlled ESR can be used to "sculpt" the profile. And an all-identical bank is not automatically robust: its peaks move to the handoffs with bulk, planes and package (section 11).
A power plane over an adjacent ground plane is a parallel-plate capacitor and a very flat current loop at the same time.
| Property | Formula | FR-4, εᵣ ≈ 4 |
|---|---|---|
| Capacitance per area | ε₀·εᵣ / h | ≈ 225 pF/in² at 4 mil · ≈ 0.9 nF/in² at 1 mil |
| Spreading inductance per square | μ₀ · h | ≈ 32 pH/sq per mil of separation |
| First cavity resonance | c / (2·a·√εᵣ) | ≈ 750 MHz for a 10 cm side |
The capacitance is small, a few nF across a board, but it has no pads, vias or package. That makes it the only board-level capacitance still working from a few hundred MHz into the GHz range, where every MLCC is inductive.
Watch the handoff. The bank's inductance resonates with the plane capacitance, making another anti-resonance. More plane capacitance moves it lower and shrinks it, and damping it needs resistance. Sandler recommends a total ESR of about half Ztarget and a worst-case Q around 1 to 1.5; Novak's matched-bypass method sets ESR to √(L/C). Thin dielectrics also lower the cavity resonances' Q. Check this region in simulation.
Your original instinct, different capacitors for different frequencies, is right at this level. It is different technologies that cover different bands, not different values in one package.
Band edges vary by design and overlap. Lower-ESL packages (0204, interdigitated) extend the MLCC band upward, and controlled-ESR parts can damp a handoff deliberately.
The value sets the low edge. The count and the mounting set the high edge.
DC bias. Class II dielectrics (X5R, X7R) lose capacitance with applied voltage. A 10 µF X5R near its rated voltage can keep less than half. Size with the derated value from the vendor's curve, not the label.
A 1.7 MHz load component, from a buck switching at 1.7 MHz or a periodic burst, needs no dedicated capacitor. Its ripple is I(1.7 MHz) × |Z(1.7 MHz)|. The bank above has 60 µF and about 83 pH, resonates near 2.2 MHz, and is under 1 mΩ at 1.7 MHz.
Placing a capacitor specifically to pull down a high-frequency resonance is a real technique, and it is consistent with everything above. Sandler's own example manages a resonance peak by adding three small ceramics, and Bogatin, Smith and Sandler describe using different values to "sculpt" the impedance profile. What separates it from the habit of "10 µF + 100 nF + 1 nF everywhere" is intent and verification.
| Situation | Why a targeted cap helps | What makes it work |
|---|---|---|
| Bank-to-plane or plane cavity anti-resonance | A cap at the hot spot adds a low-L path exactly where the peak lives | Low mounted L at that location, and enough ESR that it does not split the peak into two new ones |
| Known EMI or noise tone (clock, SerDes, switcher harmonic) | Its SRF can sit on the tone for a deep local notch | Check tolerance, DC-bias and temperature drift, and the peaks it creates on either side |
| Package or die resonance | Board caps rarely reach it; controlled-ESR parts can damp it | Controlled ESR rather than lowest ESR |
| Different package sizes | A lower-ESL package (0201, 0204, interdigitated) really does extend coverage upward | The value differs because the package differs. FPGA vendor tables mix values this way. |
How the two views fit together. Default: one value, the largest in the lowest-ESL package, enough of them, spread around the IC. Exception: a specific peak found in simulation or measurement, fixed with a deliberately chosen part whose ESR and placement are checked. Both camps agree on the last step: simulate and measure the whole PDN, because any combination can work or fail depending on Q and layout.
| Source | Position |
|---|---|
| Bogatin, Smith, Sandler · The Myth of Three Capacitor Values (Signal Integrity Journal, 2020) | The three-value rule is a through-hole legacy. "A 10 and 0.1 uF MLCC capacitor will have exactly the same high frequency impedance." Different values create parallel resonance peaks. Identical values are not automatically more robust; analyze the system. |
| Archambeault (IBM) · Eliminating the Myths about PCB Power/Ground Plane Decoupling | Measured: "a single value of capacitance is better than multiple values." Mixing 0.01 µF and 330 pF worsened 75–200 MHz. Use the largest C in the chosen package; mounting inductance dominates. |
| Archambeault, Kim, Connor, Fan · IEEE EMC Society Design Tips | Mounted L of 2–3 nH is typical even for 0402. Clustered caps do not divide inductance; spread them around the IC. |
| Sandler · PDN Basics: Paralleling Tantalum and Ceramic Capacitors Can Be Risky (Electronic Design) | Paralleling different low-ESR ceramics "can lead to disastrous results." Target Q ≈ 1–1.5 and total ESR ≈ 50 % of Ztarget. Adds small caps to manage a specific peak. |
| Novak et al. (Sun, Sanmina, AVX) · Distributed Matched Bypassing | Use the highest C per case size. Banks of different values are flat when ESR matches √(L/C); low-ESR parts leave ripple. Minimize the connecting inductance. |
| ROHM · TechWeb: antiresonance | Identical parts lower impedance everywhere. Adding a smaller value lowers HF impedance but creates antiresonance that can worsen EMI. Choose an added value by the noise frequency. |
| Analog Devices · MT-101 Decoupling Techniques | Electrolytic plus a small ceramic at the pins, citing the small part's lower ESL. Precision-analog context with leaded-era reasoning; does not address anti-resonance. |
"I design decoupling to a target impedance, V × ripple / ΔI, held from where the VRM loop runs out to where plane and package capacitance take over. A real MLCC is a series RLC: below self-resonance its capacitance sets |Z|, above it the inductance does, and that inductance comes from the current loop, meaning the package plus pads, vias and plane spacing, not the value. So I use the largest value that fits the lowest-inductance package at my voltage, after DC-bias derating, and parallel enough of them to meet both the capacitance limit at the low edge and the inductance limit at the high edge. Identical parts avoid peaks between themselves, while low-ESR values mixed in one package create tank anti-resonances. If simulation shows a specific peak, I add a targeted part with controlled ESR at the hot spot and verify it. Different bands are covered by different technologies: bulk below, the MLCC bank in the middle, planes and package above. Most of the remaining effort goes into mounting inductance and stackup, verified in simulation and with a VNA."
"No. That's sculpting a specific peak, and Sandler, Bogatin and Smith all describe it. What I avoid is the reflexive three-value pattern. A targeted part needs low mounted inductance at the hot spot and enough ESR not to split the peak in two, and I'd confirm it in simulation and with a VNA."
"Partly habit from leaded parts, where ESL tracked size. Partly because 100 nF used to be the largest value in the smallest package. It also works when ESR is high enough to damp the peak or the parts really are in different packages. I'd simulate it rather than copy it."
"The rail cares about |Z|, not its phase. Above SRF |Z| is 2πfL, so the bank keeps working as long as N parts keep L low enough to stay under target. Most of a bank's useful band is above its SRF."
"A thin power/ground pair is a capacitor with almost no inductance, about 32 pH per square per mil, so it covers the band above where MLCCs stop working. Two pairs halve the inductance, and a pair near each surface shortens the cap vias."
"A GaN half-bridge's input caps are the same problem with a tighter budget. The power loop needs to be under about 1 nH, so the cap's package and placement right at the switch matter more than its value."