Power integrity · decoupling
Ten of one value in parallel, or one each of 10 µF, 100 nF and 1 nF? Every curve on this page comes from the same series-RLC model of a mounted 0402 MLCC, so you can change the inputs and watch the argument hold or break.
The usual advice is mostly right. In one package size, every MLCC has about the same inductance, so above its self-resonant frequency (SRF) the value stops mattering. Mixing values buys little coverage and creates anti-resonance peaks between the resonances. Paralleling identical parts lowers inductance, capacitance and resistance together with no peaks. Your instinct is right one level up: different technologies and packages (bulk, MLCC, plane, package, die) do cover different bands.
The peaks scale with 1/ESR, so the real issue is high Q rather than mixing as such. A deliberately chosen, damped part placed on a specific peak is a valid fix. Section 15 of the MLCC Decoupling Primer lists sources on both sides.
Every MLCC on a board is capacitance C in series with resistance (ESR) and inductance. The inductance is the part's own ESL plus the mounting inductance of pads, vias and the path to the planes. Its impedance is:
Below the SRF the 1/(2πfC) term dominates and impedance falls. At the SRF the two reactances cancel and only ESR is left. Above it, 2πfL dominates and impedance rises. Here are four values in the same 0402 package with the same 1 nH mounted inductance.
The dotted line is 2πf·L for L = 1 nH alone. Above each SRF, every curve lands on it. A bigger C only moves the dip lower and further left. It goes inductive sooner, and then it is the same part as the others.
Inductance is a property of the current loop: how much area and length the current encloses on its way from the plane, up a via, across the part and back down. It depends on shape, not on what is inside the part.
A 100 nF and a 1 µF in 0402 have the same outside dimensions, terminations, pads and vias. The capacitance difference comes from more and thinner internal electrode layers and the dielectric. The loop the current rides through is the same, so the inductance is the same.
Typical numbers: an 0402 body is about 0.3–0.4 nH. The mounted loop, with pads, vias and the trip to the planes, is usually 0.5–3 nH, higher when the planes sit deep in the stack. The mounting is often the bigger half.
Shorter vias, via-in-pad, and a thinner dielectric between the planes shrink the loop. That is where decoupling performance is won.
Approach A is ten 1 µF 0402s in parallel. Approach B is one each of 10 µF, 100 nF and 1 nF, the "one value per decade" layout. The dashed line is the target impedance. Change anything and the plot and table recompute.
| Metric | A | B |
|---|
Model only: caps in parallel on an ideal plane pair. No VRM, plane capacitance, spreading inductance or package. ESR per value is a typical 0402 X5R/X7R figure. Use it to see shapes and ratios, not to sign off a design.
Things to notice with the default inputs:
Between 1.6 and 16 MHz, B is an L in parallel with a C: a tank circuit. A tank has a parallel resonance where impedance peaks instead of dipping.
Two parallel branches have a peak where their reactances cancel around the loop, so the current circulates between the two parts instead of being supplied by them.
For the default bank, with L₁ = L₂ = 1 nH and C₂ = 100 nF:
The peak is proportional to 1/ESR. That is why low-ESR MLCCs make it worse: the better the parts, the sharper and taller the peak. Identical parts in parallel have identical SRFs, so no branch is ever inductive while another is capacitive, and there is no tank.
N identical branches in parallel act as one part with C × N, L ÷ N and ESR ÷ N. The SRF stays put, because √(L/N · C·N) = √(L·C). The whole curve drops by a factor of N at every frequency, with the same shape.
1 µF 0402 parts, mounting L from the slider above. Each step down is the same shape. Real boards fall short of a perfect N: caps clustered on one side add capacitance but cut the inductance the IC sees much less than L ÷ N. Spreading them around the IC works better.
| Band (typical) | What covers it | Why it is a different tool |
|---|---|---|
| DC – ~100 kHz | VRM control loop | Active regulation |
| ~10 kHz – 1 MHz | Bulk polymer, tantalum, aluminium | High C, higher ESR, larger package. The ESR damps resonances. |
| ~100 kHz – 100 MHz | MLCC bank | Paralleled to target. Package and mounting set the top. |
| ~100 MHz – 1 GHz | Plane-pair capacitance, package caps | No vias or pads, so very low inductance |
| > 1 GHz | On-die capacitance | Inside the loop of the switching current |
"Above self-resonance an MLCC is an inductor, and that inductance is set by the package and the mounting, not the capacitance. So in one package, a smaller value adds almost nothing, and mixing values can create anti-resonance peaks between their resonances. I size the bank to a target impedance with the largest value that fits the package and voltage, parallel enough of them, put my effort into via placement and plane spacing, and verify the PDN in simulation and with a VNA."
"Partly habit from leaded parts, where ESL tracked size. Partly because 100 nF used to be the largest value in the smallest package. The mix also works when the ESR is high enough to damp the peak, or when the parts really are in different packages. I'd check it in simulation rather than copy it."
"Different technologies across bands: bulk, MLCC, plane, package. Lower-ESL packages for the high end. Or a deliberate damping choice I've simulated."
"A GaN half-bridge's input caps are the same problem with a tighter budget. The power loop needs under about 1 nH, so the cap's package and its placement right at the switch matter more than its value."