Undervoltage, overvoltage and overcurrent protection

How input-window lockout and current limiting are built from comparators, dividers and a pass element, with the equations needed to size them.

UV/OV window comparator

The input rail is scaled by a resistor divider and compared against an internal bandgap reference. The pass FET (or the converter's switching) is enabled only while V_IN sits above the UV threshold and below the OV threshold. One three-resistor string sets both limits.

Figure 1. Window comparator. Blue blocks are typically inside the controller IC (eFuse, hot-swap controller, ideal-diode controller or PMIC); R1–R3 are external.

How it works

The UV comparator's output goes high once the UV sense node rises above V_REF. Below that, the logic holds EN low and the gate is pulled down.
The OV comparator watches the lower tap. When the OV sense node exceeds V_REF, it asserts OV and the logic turns Q1 off, isolating the load.
The logic ANDs the two, applies a deglitch filter, and drives the gate through a charge pump (an N-FET on the high side needs gate drive above V_IN).
Because R1 sits above both taps, the UV tap always reads higher than the OV tap. That ratio is what spreads the two thresholds apart.

V_UV = VREF × (R1 + R2 + R3) / (R2 + R3) V_OV = VREF × (R1 + R2 + R3) / R3

Worked example: 12 V automotive input

Target UV ≈ 6 V and OV ≈ 18 V with V_REF = 1.2 V. That needs a total-to-(R2+R3) ratio of 5 and a total-to-R3 ratio of 15.

Pick R3 = 10 kΩ → R_total = 150 kΩ R2 + R3 = 30 kΩ → R2 = 20 kΩ R1 = 150 − 30 = 120 kΩ Divider current at 12 V ≈ 80 µA

Check the result against worst-case reference tolerance and 1% resistors. The UV trip must stay below the minimum cold-crank voltage you need to ride through, and the OV trip must stay below the downstream parts' absolute-max rating with margin for the trip delay.

Hysteresis

A converter starting up draws current, which drops V_IN across the source impedance. Without hysteresis that drop re-trips the UVLO and the system oscillates on and off. Many parts solve this with a switched current sink on the EN/UVLO pin, which lets the hysteresis be set independently of the threshold.

Figure 2. Current-sink hysteresis. While the device is off, I_HYS pulls the pin down, so V_IN must rise higher to turn on. Once enabled, the sink turns off and the pin jumps up, so V_IN must fall further to turn off.

V_FALL = VREF × (1 + R_TOP/R_BOT) V_RISE = V_FALL + I_HYS × R_TOP ΔV_HYS = I_HYS × R_TOP

Example

V_REF = 1.2 V, I_HYS = 20 µA. Target turn-on at 7 V and turn-off at 6 V.

R_TOP = 1 V / 20 µA = 50 kΩ R_TOP/R_BOT = 6/1.2 − 1 = 4 R_BOT = 12.5 kΩ

Figure 3. The loop the input must traverse to turn on and off.

OV pins often have fixed internal hysteresis (a few percent of the threshold) rather than a programmable current, since OV recovery is less sensitive to source impedance.

Timing and fault response

Deglitch. Comparator outputs are filtered, typically for a few µs to tens of µs, so ringing and ESD-coupled spikes don't cause nuisance trips. A small capacitor on the sense node adds external filtering but also slows the real trip.
OV speed. The OV path is usually faster than UV, because a slow OV response lets the transient reach the load. Fast surges still need a TVS or a surge-stopper clamp; the lockout protects against sustained overvoltage, not nanosecond edges.
Recovery. Auto-retry re-enables once V_IN returns inside the window (with soft-start restarting from zero). Latch-off requires an EN toggle or power cycle.
Internal UVLO. Separate from the programmable window, almost every IC has a fixed UVLO on its own supply so the gate driver never runs at insufficient V_GS, which would leave the FET in its linear region and overheat it.

Overcurrent protection

OCP measures load current, compares it to a limit, and then either cuts off the pass element or regulates it to cap the current. The sensing method and the response after detection matter more than the comparator itself.

Figure 4. High-side shunt OCP as used in eFuses and hot-swap controllers. The comparator path detects the fault; the dashed path (where present) actively limits current while the timer on C_T decides how long that is allowed to last.

How it works

Load current develops a small voltage across R_SENSE, measured with Kelvin taps so trace and solder resistance don't add error.
The current-sense amplifier rejects the large common-mode voltage (V_IN) and amplifies the differential signal.
When the amplified signal crosses V_TH, the fault logic starts the timer. If the overload clears before the timer expires, nothing happens; this lets inrush and brief load steps through.
If the timer expires, Q1 is turned off and the part either latches or retries after a cooldown period.
In parts with a linear current limit, an error amp also pulls the gate down to hold current at I_LIM during the timer window, so the source never sees more than the limit.

I_LIM = V_TH / (G × R_SENSE) P_SENSE = I² × R_SENSE P_Q1 (during limit) ≈ (VIN − VOUT) × I_LIM

Example: 10 A limit

R_SENSE = 2 mΩ → V_SENSE = 20 mV at 10 A G = 50 → V_TH = 1.0 V P_SENSE at 10 A = 0.2 W Hard short at 14 V: P_Q1 ≈ 14 V × 10 A = 140 W

That last number is the reason for the timer. Q1 can only dissipate 140 W for as long as its SOA curve allows at the expected case temperature, often a few milliseconds. Size C_T so the fault time falls inside the SOA with margin, and make sure it is still longer than the inrush period charging the output capacitance.

Response modes

Mode	Behaviour	Typical use
Circuit breaker	Turns off as soon as the threshold is crossed (after a short deglitch). No current regulation.	Simple load switches, fast fuse replacement
Constant current + timer	Regulates current at I_LIM; turns off if it persists past the timer.	Hot-swap, eFuses, capacitive loads
Foldback	Allowed current drops as V_OUT collapses, reducing FET dissipation into a short.	Linear regulators, hot-swap with tight SOA
Hiccup	Shuts down and periodically retries, keeping average power low during a persistent short.	DC/DC converters, PoE, auto-retry eFuses
Cycle-by-cycle	Terminates each switching cycle when the inductor or switch current hits the peak limit.	Switching regulators (peak current-mode control)

Figure 5. Foldback cuts short-circuit current to I_SC, trading lower FET stress for a startup risk: a heavy or capacitive load can get stuck on the foldback curve and never come up.

Current sensing methods

Method	Strengths	Weaknesses
Shunt resistor	Most accurate (≈1–2%), low tempco, independent of FET.	I²R loss, board area, needs Kelvin layout and a CSA with adequate common-mode range.
R_DS(on) sensing	No extra loss or parts.	R_DS(on) varies part to part and rises roughly 1.5–2× from 25 °C to 125 °C, so the limit is loose.
Inductor DCR	Lossless in buck converters; RC network matches the L/DCR time constant.	Copper tempco (~0.39%/°C) needs compensation; sensitive to inductor tolerance.
SenseFET / current mirror	Integrated in eFuses and smart high-side switches; scaled replica of main current.	Accuracy typically 5–15%, depends on matching and low-current behaviour.

Design checklist

Stack reference, resistor and temperature tolerances so the worst-case UV and OV trip points still fall inside the system's valid operating range.
Use high-value dividers to cut quiescent current only after checking pin leakage error and noise pickup; add a small filter cap at the sense node if needed.
Confirm the UV hysteresis exceeds the input sag caused by the startup current times the source and harness impedance.
Set the OCP limit above the worst-case normal peak (including inrush into C_OUT) but below the source, connector and trace ratings.
Check the pass FET's SOA at the worst-case V_DS × I_LIM for the full timer duration, at maximum ambient.
Route Kelvin sense traces as a tight pair directly from the shunt pads, away from switching nodes.
In switching converters, verify the leading-edge blanking time so the switch-on current spike doesn't trip cycle-by-cycle limiting.
Decide on latch versus auto-retry per rail, based on how the system should recover from a persistent fault.