Signaling · line codes

PAM3 Signaling Primer

Three-level pulse amplitude modulation from first principles: what it buys, what it costs, how bits get packed into trits, and how the receiver gets them back. Every section has a worked example with real numbers. Mappings marked illustrative show the method; the normative tables live in the standards.

The one-paragraph answer

PAM3 sends one of three voltage levels per symbol, usually written −1, 0, +1. Each symbol (a "trit") can carry up to log₂3 ≈ 1.585 bits, so for a given bit rate the symbol rate drops by about 37% compared with NRZ, and the channel only has to pass a Nyquist frequency about 37% lower. The price is that the full swing is split into two stacked eyes, each half the height of an NRZ eye: a 6.02 dB SNR penalty. Because three isn't a power of two, bits are packed in blocks: 3 bits in 2 trits (3B2T), 4 in 3 (4B3T), 11 in 7 (11B7T). PAM3 is the choice when the channel's loss at the NRZ Nyquist frequency costs more than 6 dB, but PAM4's 9.5 dB penalty, tighter linearity and worse DFE error propagation are too much.

01The idea

A binary (NRZ, or PAM2) link spends each unit interval (UI) choosing between two levels. PAM3 adds a third level halfway between them. Differentially, the levels are typically −A, 0, +A; the "0" is a real transmitted state (both legs at common mode), not an absence of signal.

The 12-bit word 0x5A7 as eight PAM3 symbols, using the illustrative 3B2T mapping from section 06. Dashed amber lines are the receiver's two decision thresholds at ±A/2.

Three words get mixed up, so pin them down early:

Symbol / trit / UI: one transmitted level held for one unit interval. GDDR7 material calls it a "symbol" (11b7s), USB4 v2 and Ethernet a "trit" or "ternary symbol" (11b/7t, 3B2T).
Baud (Bd): symbols per second. Bit rate = baud × bits carried per symbol after coding.
Nyquist frequency: baud ÷ 2. This is the highest fundamental the channel must pass (a −1,+1,−1,+1 pattern), and where you read channel insertion loss.

02Bits per symbol

An M-level symbol carries at most log₂M bits. For M = 3 that's 1.58496 bits. A whole bit can't be split, so practical codes group k bits into n trits, which needs 2^k ≤ 3ⁿ. The code then carries k/n bits per trit, and its efficiency is (k/n) ÷ 1.585.

Scheme	Levels M	Bits/symbol (max)	Eyes	Eye height vs NRZ	SNR penalty	Slicers
NRZ / PAM2	2	1.000	1	1	0 dB	1
PAM3	3	1.585	2	1/2	6.02 dB	2
PAM4	4	2.000	3	1/3	9.54 dB	3
PAM8	8	3.000	7	1/7	16.9 dB	7

The penalty column is 20·log₁₀(M−1): with the peak-to-peak swing fixed, M levels leave M−1 gaps, each 1/(M−1) of the swing.

03Bandwidth: the reason it exists

Copper and PCB channels lose more at higher frequency (skin effect grows as √f, dielectric loss as f). If you need a fixed bit rate, the only way to lower the frequency the channel must pass is to send fewer symbols per second, which means more bits per symbol.

Worked example · one 40 Gb/s lane, three ways

Scheme	Coding	Baud	UI	Nyquist
NRZ	1 bit/sym	40 GBd	25.0 ps	20.0 GHz
PAM3 (USB4 v2)	11b/7t = 1.571 b/sym	25.6 GBd	39.1 ps	12.8 GHz
PAM4	2 b/sym	20 GBd	50.0 ps	10.0 GHz

PAM3 raw rate = 25.6 GBd × 11/7 = 40.23 Gb/s (USB4 Gen 4: two lanes per direction → 80 Gb/s) Theoretical floor = 40 Gb/s ÷ log₂3 = 25.24 GBd (11b/7t gets within 1.4% of it)

Now give the channel a loss slope. Say a USB-C cable plus host traces lose roughly 1.2 dB/GHz near these frequencies (a round number for the arithmetic, not a spec value):

NRZ : 20.0 GHz × 1.2 = 24.0 dB loss + 0.00 dB level penalty = 24.0 dB PAM3: 12.8 GHz × 1.2 = 15.4 dB loss + 6.02 dB level penalty = 21.4 dB PAM4: 10.0 GHz × 1.2 = 12.0 dB loss + 9.54 dB level penalty = 21.5 dB

On this crude budget PAM3 and PAM4 tie and both beat NRZ by about 2.5 dB. The tie is why the PAM3-vs-PAM4 choice is decided by second-order effects (section 14): crosstalk, linearity, slicer count, DFE error propagation and jitter. The loss saved by dropping the baud has to exceed the level penalty, or the multi-level scheme loses.

04Eye height and the 6 dB penalty

Idealized eyes at the same peak-to-peak swing. PAM3 stacks two eyes, PAM4 three. Each PAM3 eye is half the NRZ height; the receiver's thresholds sit in the middle of each eye.

With Gaussian noise of standard deviation σ and level spacing d, a symbol error happens when noise exceeds d/2 toward a neighbor. Outer levels have one neighbor, inner levels two. For equiprobable M-PAM:

P_sym = 2·(1 − 1/M) · Q( d / 2σ ) PAM3: P_sym = (4/3) · Q( d / 2σ ), d = A, levels at −A, 0, +A

Worked example · same transmitter swing, same noise

Receiver sees ±400 mV extremes (800 mV peak-to-peak differential) and σ = 30 mV of noise.

NRZ: levels −400 and +400, d = 800 mV. d/2σ = 13.3. Q(13.3) ≈ 7×10⁻⁴¹. Errors never happen.
PAM3: levels −400, 0, +400, d = 400 mV. d/2σ = 6.67. Q(6.67) = 1.31×10⁻¹¹, so P_sym = 4/3 × 1.31×10⁻¹¹ = 1.7×10⁻¹¹.
What that 6 dB means: to give PAM3 the NRZ margin you would need 800 mV per eye, i.e. 1.6 V swing, twice the voltage. Twice the voltage is +6.02 dB.

This comparison is unfair to PAM3, because at the same bit rate it runs at a lower baud: the channel loses less, and the receiver's noise bandwidth is narrower (noise power ∝ bandwidth, so 0.64× the baud cuts integrated white noise by about 1.9 dB). The level penalty is a fixed 6 dB; the bandwidth savings depend on the channel.

Bit errors vs symbol errors

A single slicer error moves a symbol to an adjacent level. How many bits that corrupts depends on the mapping. Good mappings make adjacent symbols differ by one bit (Gray-like), so BER ≈ P_sym ÷ (bits per symbol). Block codes like 3B2T and 11B7T can't be perfectly Gray, so some single trit errors flip 2–3 bits. This is one reason the PAM3 standards pair the line code with FEC.

05Packing bits into trits

Every block code is a choice of k and n with 2^k ≤ 3ⁿ. Leftover codewords (3ⁿ − 2^k) aren't wasted: designs use them for control characters, comma/alignment codes, DC-balance alphabets, or to steer away from codewords that hurt the eye.

Code	2^k data words	3^n codewords	Spare	Bits/trit	Efficiency	Used in
1B1T	2	3	1	1.000	63.1%	AMI (bipolar), MLT-3-style codes
3B2T	8	9	1	1.500	94.6%	100BASE-T1, 1000BASE-T1; GDDR7 "3b2s"
4B3T	16	27	11	1.333	84.1%	10BASE-T1L; ISDN U-interface (MMS43)
8B6T	256	729	473	1.333	84.1%	100BASE-T4; proposed for 100BASE-T1L
11B7T	2,048	2,187	139	1.571	99.1%	USB4 v2 (11b/7t), GDDR7 data (11b7s)
19B12T	524,288	531,441	7,153	1.583	99.9%	Theoretical; encoder too large

The trade is visible in the table. Codes with many spare codewords (4B3T, 8B6T) can enforce DC balance and still have room for control; dense codes (11B7T) get almost all of log₂3 but have little room for anything else, so DC balance and error control move to a scrambler and FEC.

063B2T, worked end to end

Two trits give a 3×3 grid of nine pairs. 3B2T uses eight and leaves one out. Leaving out the center pair (0,0) is the natural choice: the eight remaining points form a ring, and walking around the ring with a 3-bit Gray sequence makes every one-level slip in either trit change exactly one bit, except slips into the excluded center.

Illustrative Gray-ring 3B2T mapping. The IEEE 802.3bw/bp tables define their own assignment (Clauses 96 and 97); verify against them before quoting a specific codeword.

Bits	Trit A	Trit B

Worked example · encode 0x5A7

Bits: 0x5A7 = 0101 1010 0111 (12 bits).
Regroup in threes: 010 · 110 · 100 · 111. Twelve bits become four 3-bit groups.
Map each group to a pair:
010→0+1110→+1+1100→0−1111→+10
Serialize: 0, +1, +1, +1, 0, −1, +1, 0 (the waveform in section 01). 12 bits in 8 symbols = 1.5 bits/symbol.
Line rate: to send 100 Mb/s this way you need 100 ÷ 1.5 = 66.67 MBd, which is exactly 100BASE-T1.

Decoding with an error

Noise pulls the 3rd symbol (+1) down past the upper threshold, so the receiver slices it as 0.
Pair 2 reads (0,+1) instead of (+1,+1). On the ring these are neighbors: 010 vs 110. One bit wrong out of 12.
Now suppose the 7th symbol (+1, first trit of pair 4) drops to 0 instead. Pair 4 reads (0,0), the unused center. The decoder knows that pair is illegal. It has to guess one of the four ring neighbors, and it can flag a code violation to the PCS. The unused codeword gives you some error detection for free.

1000BASE-T1 uses the same 3B2T mapper with much heavier machinery around it; the frame arithmetic is in section 13.

074B3T and DC balance

Many PAM3 links are AC-coupled through transformers or capacitors, and on single-pair Ethernet with power (SPoE) the data shares the pair with DC power through coupling caps and inductors. An AC-coupled link can't carry a DC average. If the data has a running DC content, the received baseline drifts ("baseline wander"), which eats into the half-eye margin.

4B3T maps 16 nibbles into the 27 three-trit words. Its 11 spare words make a DC-balance trick possible: give nibbles with non-zero weight (sum of trits) two versions, one positive and one negative, and let the encoder pick whichever pulls the running digital sum (RDS) back toward zero. 10BASE-T1L uses a 4B3T code with running disparity at 7.5 MBd; the ISDN U-interface's MMS43 is the classic ancestor.

Worked example · RDS with an illustrative 4B3T alphabet

Nibble	Positive version (weight)	Negative version (weight)
0x0	+ 0 − (0)	same (balanced)
0x5	+ + 0 (+2)	− − 0 (−2)
0x9	0 + 0 (+1)	0 − 0 (−1)
0xC	+ − + (+1)	− + − (−1)

Rule: if RDS ≤ 0, send the positive version; if RDS > 0, send the negative one. Send nibbles 5, 9, C, 0, 5:

Nibble	RDS before	Chosen word	RDS after	RDS if always positive
5	0	+ + 0	+2	+2
9	+2	0 − 0	+1	+3
C	+1	− + −	0	+4
0	0	+ 0 −	0	+4
5	0	+ + 0	+2	+6

With disparity control RDS stays within a small window; without it RDS ramps without limit. The decoder doesn't need to know RDS: both versions of a word decode to the same nibble.

How much baseline wander costs

Model the AC coupling as a first-order high-pass with corner f_c. A level held for N symbols of period T droops by about 1 − e^(−2π·f_c·N·T).

10BASE-T1L: T = 1/7.5 MBd = 133 ns. Take f_c = 10 kHz, N = 100 symbols of DC-heavy data: droop ≈ 1 − exp(−2π · 10⁴ · 100 · 133×10⁻⁹) = 1 − e^(−0.084) ≈ 8% of A Half-eye margin is A/2, so 8% of A consumes 16% of the margin.

A bounded RDS caps how long DC content can build, so the droop stays small regardless of the data.

0811B7T: near-perfect packing

3⁷ = 2,187 and 2¹¹ = 2,048, so 11 bits fit in 7 trits with 139 codewords to spare. At 1.571 bits/trit it's 99.1% of the PAM3 limit. USB4 Version 2.0 uses it (11b/7t) at 25.6 GBd, and GDDR7 uses an 11b7s encoder for data alongside smaller 3b2s encoders.

Worked example · 11B7T by radix conversion

The simplest mental model: treat the 11 bits as an integer and write it in base 3 with 7 digits. Digit 0, 1, 2 maps to level −1, 0, +1.

bits = 101 1001 1101 = 1024+256+128+16+8+4+1 = 1437 1437 ÷ 729 (3⁶) = 1 rem 708 708 ÷ 243 (3⁵) = 2 rem 222 222 ÷ 81 (3⁴) = 2 rem 60 60 ÷ 27 (3³) = 2 rem 6 6 ÷ 9 (3²) = 0 rem 6 6 ÷ 3 (3¹) = 2 rem 0 0 ÷ 1 (3⁰) = 0 base-3 digits : 1 2 2 2 0 2 0 levels : 0 +1 +1 +1 −1 +1 −1 check : 729 + 2·243 + 2·81 + 2·27 + 0 + 2·3 + 0 = 1437 ✓

Radix conversion is correct but bad for errors and hardware. A one-level slip in the top trit changes the integer by 729, which flips many bits; and a 2,048-entry divide chain is slow at 25+ GBd.

How hardware actually builds it

Published analyses describe partitioned encoders: split the 11 bits into three 3-bit groups plus 2 leftover bits, encode each group with 3B2T (6 trits), and use the 7th trit plus the unused center pairs to carry the leftover 2 bits. One construction that works:

Leftover bits 00, 01, 10 → 7th trit = −1, 0, +1; the three groups use normal 3B2T. That covers 3 × 8³ = 1,536 words.
Leftover bits 11 → an escape: at least one of the three pairs takes the otherwise-unused (0,0) code, and the remaining positions carry the 9 bits. There are 3 × (9³ − 8³) = 651 such codewords, more than the 512 needed.
Result: most single-trit errors stay inside one 3B2T group (1–2 bit errors), and the encoder is small lookup tables instead of a divider.

This shows the principle. The exact USB4 v2 and JESD239 tables differ and are what to check before quoting codewords.

09Three levels that aren't PAM3

Interviewers sometimes probe whether you know these apart. All use three voltage levels, but each carries only one bit per symbol:

Code	Rule	Bits/symbol	Why use it
MLT-3 (100BASE-TX)	Bit 1: step to the next level in the cycle 0 → + → 0 → − → 0. Bit 0: hold.	1	Spectral shaping: the fastest pattern (all 1s) takes 4 bits per full cycle, so the fundamental is bit rate ÷ 4.
AMI / bipolar (T1, E1)	Bit 0 → 0. Bit 1 → alternating + and −.	1	Zero DC; a violation of the alternation flags an error or carries framing (B8ZS).
Duobinary	Binary data through a deliberate 1 + D response; the receiver sees three levels.	1	Halves the needed bandwidth by controlled ISI; appears inside receivers and optical links.

Worked example · MLT-3 on 100BASE-TX

100 Mb/s of data goes through 4B5B → 125 Mb/s on the wire.
Bits 1 1 1 1 0 1 1, starting at 0: levels + 0 − 0 0 + 0.
Worst-case fundamental: a run of 1s gives the cycle 0 + 0 − every 4 bits → 125 ÷ 4 = 31.25 MHz. NRZ at 125 Mb/s would have a 62.5 MHz fundamental.
MLT-3 has three levels but sends one bit per baud. PAM3 proper sends up to 1.585.

10The transmitter

Producing three levels is mostly a driver-segmentation problem.

Differential current-mode (CML) driver: split the tail current into two halves with separate switch pairs. Both steer the same way → ±A. They steer opposite ways → the currents cancel, the output sits at 0 differential. Matching the two halves sets how well the 0 level lands in the middle.
Voltage-mode (SST) driver: many parallel slices, each connecting the pad to the high or low rail through a series resistor. Pull-up slices, pull-down slices, or a 50/50 split for the middle level. Output impedance stays matched because the same number of slices is on in every state. GDDR7's PAM3 is single-ended, so the "0" is a middle voltage relative to the termination, not a differential zero.
FFE (feed-forward equalization): the same pre-/post-cursor taps as NRZ, applied to the level sequence. USB4 v2 defines 42 transmitter presets for Gen 4; NRZ Gen 2/3 used 16.

Worked example · level mismatch

Measured mean levels at the far end: −392 mV, +20 mV, +404 mV.

upper eye = 404 − 20 = 384 mV lower eye = 20 − (−392) = 412 mV mismatch ratio (min/max) = 384 / 412 = 0.932 ideal middle level = (404 + (−392)) / 2 = +6 mV → 14 mV off center

The upper eye has lost 14 mV of height (about 7% of its half-eye margin) to a pure DC error. Both eyes have to pass, so the worse one sets the margin. PAM3 has only one inner level to place, which is one reason its linearity requirement is easier than PAM4's two. USB4 v2 compliance includes a Level_Mismatch measurement comparing the top and bottom eye openings; use the spec's own formula when you quote a pass/fail limit.

11The receiver: slicers, CDR, DFE

Two slicers

After CTLE (and often an ADC + DSP at Ethernet rates), the receiver compares each sample against two thresholds at ±A/2:

v > +A/2 → +1 −A/2 ≤ v ≤ +A/2 → 0 v < −A/2 → −1

The thresholds must track the actual received amplitude, so the receiver runs an AGC or adapts the thresholds. A gain error of 10% moves an optimum ±A/2 threshold by 5% of A, which is 10% of the half-eye.

Crossing families and CDR jitter

NRZ has one kind of transition. PAM3 has three distances: full swing (−1↔+1) and two half swings (−1↔0, 0↔+1). They cross the decision thresholds at different times, so a CDR that watches all crossings sees extra data-dependent jitter.

First-order (RC-limited) edges. The −1→+1 edge crosses −A/2 early and +A/2 late; the −1→0 edge crosses −A/2 at its own midpoint.

Worked example · how big is the skew?

Edges settle as v(t) = v_start + Δv·(1 − e^−t/τ).

Half swing −1→0 crosses −A/2 at 50% of its step: t = τ·ln 2 = 0.693 τ Full swing −1→+1 crosses −A/2 at 25% of its step: t = τ·ln(4/3) = 0.288 τ Skew between the two families = 0.405 τ USB4 v2 lane: 25.6 GBd → UI = 39.1 ps Assume 10–90% rise of 20 ps → τ = 20 / 2.2 = 9.1 ps Skew = 0.405 × 9.1 = 3.7 ps ≈ 9.5% of a UI

Common fixes: drive the phase detector only from transitions whose crossings line up (for example, full-swing edges at the zero crossing, or each half-swing edge at its own threshold), or use a baud-rate (Mueller-Müller) CDR that samples once per UI and doesn't look at edges at all.

DFE

A decision-feedback equalizer subtracts the post-cursor ISI of symbols already decided: v'_n = v_n − h₁·ŷ_n−1 − h₂·ŷ_n−2 … With three possible previous decisions, a speculative ("loop-unrolled") first tap needs 3 × 2 = 6 comparators instead of NRZ's 2 × 1 = 2; PAM4 needs 4 × 3 = 12. When a decision is wrong, the subtraction is wrong too and can cause the next decision to be wrong: error propagation. With large h₁ these errors come in bursts of alternating sign.

12Precoding against DFE bursts

USB4 v2 combines FEC with precoding to reach its target BER (the published USB4 v2 analyses quote raw trit error rates around 10⁻⁸ on worst-case channels before correction). The mod-3 precoder 1/(1+D) turns a burst of alternating-sign errors into just two errors, one at each end.

Transmit: p[n] = (x[n] − p[n−1]) mod 3 x, p ∈ {0,1,2} ↔ levels {−1,0,+1} Receive : x̂[n] = (p̂[n] + p̂[n−1]) mod 3

Worked example · a 4-symbol DFE burst

n	0	1	2	3	4	5	6	7
data x	1	2	0	2	1	1	0	2
precoded p	1	1	2	0	1	0	0	2
burst error e	0	0	−1	+1	−1	+1	0	0
received p̂	1	1	1	1	0	1	0	2
decoded x̂	1	2	2	2	1	1	1	2

Check one: x̂[3] = (p̂[3] + p̂[2]) mod 3 = (1 + 1) mod 3 = 2 = x[3]. Inside the burst, consecutive errors are +1 and −1, so they cancel in the sum. Four wrong symbols become two wrong data trits (n = 2 and n = 6). Without precoding all four would be wrong, and the FEC would have to correct twice as much.

The cost: an isolated (non-burst) error now causes two data errors instead of one. Precoding pays off only when DFE bursts dominate, which is why it is a configurable option in links that use it.

13Where PAM3 is used

Standard	Baud	Coding stack	Data rate	Medium / notes
10BASE-T1L (802.3cg)	7.5 MBd	Scrambler + 4B3T	10 Mb/s	One pair, ≥1 km on 18 AWG; 1.0 or 2.4 Vpp; SPoE optional. Industrial sensors.
100BASE-T1 (802.3bw)	66.67 MBd	4B3B + scrambler + 3B2T	100 Mb/s	Automotive single pair, 15 m, full-duplex with echo cancellation.
1000BASE-T1 (802.3bp)	750 MBd	80B/81B + RS(450,406) + scrambler + 3B2T	1 Gb/s	Automotive single pair, 15 m.
100BASE-T4 (1995)	25 MBd/pair	8B6T	100 Mb/s	Cat 3, three pairs carry data; historic.
USB4 v2 Gen 4	25.6 GBd	11b/7t + precoding + FEC	40 Gb/s/lane	USB-C; 80 Gb/s symmetric, 120 Gb/s asymmetric.
GDDR7 (JESD239)	≈21–32 GBd	11b7s, 3b2s (+ CRC, on-die ECC)	32–48 Gb/s/pin	Single-ended, bidirectional burst bus; NRZ at low speed.

Worked example · 1000BASE-T1 frame arithmetic

45 blocks × 81 bits (80B/81B) = 3,645 bits + 9 bits OAM = 3,654 bits = 406 RS symbols × 9 bits + RS parity 44 symbols × 9 = 396 bits RS frame = 4,050 bits = 450 symbols → RS(450,406), corrects 22 symbols 3B2T: 4,050 bits ÷ 3 × 2 = 2,700 PAM3 symbols per frame Payload per frame = 45 × 80 = 3,600 bits Frames per second = 750×10⁶ ÷ 2,700 = 277,778 Data rate = 277,778 × 3,600 = 1.000 Gb/s ✓

The 9-bit RS symbol was picked because it lines up with 3B2T: three 3-bit groups make one RS symbol, so a single PAM3 pair error damages at most one RS symbol.

Worked example · 100BASE-T1, the link on your radar board

MII: 4 bits × 25 MHz = 100 Mb/s 4B3B regroup: 3 bits × 33.33 MHz = 100 Mb/s (same bits, 3-wide) 3B2T: 2 trits per 3 bits → 33.33 MHz × 2 = 66.67 MBd Nyquist = 33.3 MHz Payload ceiling = 100 Mb/s ÷ 8 = 12.5 MB/s

That 12.5 MB/s ceiling is the 88Q1010-class 100BASE-T1 limit from your controller-board story. The physical link under it was PAM3 at 66.67 MBd, which is how a 100 Mb/s automotive link fits a 33 MHz Nyquist on one unshielded pair with margin for automotive EMC. It's a good bridge if the PAM3 question comes up.

Worked example · 10BASE-T1L on a robot or factory floor

10 Mb/s × 3/4 (4B3T) = 7.5 MBd, Nyquist 3.75 MHz Tx 2.4 Vpp → levels ≈ −1.2, 0, +1.2 V; eye spacing 1.2 V Tx 1.0 Vpp → levels ≈ −0.5, 0, +0.5 V; used where intrinsic-safety energy limits apply

Low baud and big levels are what buy 1 km reach. The 4B3T disparity control keeps the baseline stable across the SPoE coupling network, and one three-trit word (all zeros) is reserved as a comma for alignment. For a robot, the same PHY family lets one pair carry both power and Ethernet to distributed sensors.

14PAM3 vs PAM4

Section 03 showed that, on a smooth loss slope, the two land within a fraction of a dB. What decides it in practice:

Factor	PAM3	PAM4
Eye height (same swing)	1/2 (−6.0 dB)	1/3 (−9.5 dB)
Baud for 40 Gb/s	25.6 GBd	20 GBd
Crosstalk sensitivity	Lower: larger eye per unit of aggressor noise	Higher; USB-C's dense connector made this decisive for USB4 v2
Linearity	One inner level to center	Two inner levels; RLM spec needed
Slicers / unrolled DFE tap 1	2 / 6	3 / 12
Bits per symbol error	~1–2 with block codes	1 with Gray coding
Bit alignment	Needs block code (3B2T, 11B7T)	Direct: 2 bits per symbol
Where it wins	Moderate loss, crosstalk-limited, cost-sensitive: USB-C, GDDR on PCB, automotive pairs	Very high loss where baud reduction matters most: 100G+ per-lane Ethernet, PCIe 6/7

GDDR6X had already used PAM4, and the industry still went to PAM3 for the JEDEC GDDR7 standard: on a single-ended memory bus with tight power and crosstalk limits, the bigger eye was worth more than the lower baud.

15Encoder playground

Data (hex) Code

Data is padded with zeros to a whole block. RDS is the running sum of levels; watch it drift on 3B2T, which has no disparity control, and stay bounded on MLT-3.

16Interview drill

Why three levels and not just run NRZ faster?

Loss and crosstalk grow with frequency. PAM3 cuts the baud by ~37% for the same bit rate, so the Nyquist frequency drops by the same factor. If the channel loses more than ~6 dB extra between the PAM3 and NRZ Nyquist frequencies, PAM3 has more margin. Lower baud also eases the CDR, clocking power and the serializer.

Where does 1.58 come from, and why don't standards hit it?

log₂3 = 1.585 bits. Bits come in powers of two and trits in powers of three, so you group them. 3B2T gets 1.5 (94.6%), 11B7T gets 1.571 (99.1%). Larger blocks get closer but the encoder grows exponentially and error behavior gets worse.

What's the SNR penalty, exactly?

20·log₁₀(M−1). For PAM3 that's 20·log₁₀2 = 6.02 dB at the same peak-to-peak swing, because each of the two eyes is half the NRZ eye. PAM4 is 9.54 dB.

How is 100BASE-T1 coded?

MII nibbles at 25 MHz are regrouped to 3-bit words (4B3B), scrambled, and each 3 bits become two PAM3 symbols (3B2T). 100 Mb/s ÷ 1.5 = 66.67 MBd, Nyquist 33.3 MHz, full-duplex on one pair with echo cancellation.

What's the problem with DC content on a PAM3 link, and how do codes fix it?

AC coupling (transformers, caps, SPoE networks) can't pass DC, so a data stream with net DC content makes the baseline wander and eats the half-eye margin. 4B3T and 8B6T use their spare codewords to keep the running digital sum bounded; dense codes like 11B7T rely on scrambling instead.

Why does PAM3 have more CDR jitter than NRZ?

Full-swing and half-swing transitions cross the decision thresholds at different times. With a first-order edge the skew is about 0.4τ, roughly 10% of a UI on a 25.6 GBd link. Fix it by choosing which transitions feed the phase detector or by using a baud-rate CDR.

Why did USB4 v2 and GDDR7 pick PAM3 over PAM4?

At their loss levels the baud saving of PAM4 didn't pay for its extra 3.5 dB of level penalty. PAM3 also tolerates crosstalk and nonlinearity better, needs fewer comparators, and has milder DFE error propagation. USB4 v2 adds precoding and FEC; GDDR7 adds CRC and on-die ECC.

What does precoding do?

A mod-3 1/(1+D) precoder at the transmitter means the receiver decodes each data trit as the sum of two adjacent decisions. Alternating-sign DFE error bursts cancel inside the sum, leaving just two errors at the burst edges. The cost is that a single random error becomes two.

How would you validate a PAM3 link on a new board?

Transmitter: level mismatch, eye height and width for both eyes, jitter, FFE presets. Channel: insertion loss at the PAM3 Nyquist, return loss, NEXT/FEXT, simulated with IBIS-AMI including the crosstalk aggressors. Receiver: stressed-eye tolerance with added crosstalk, and pre-FEC symbol error rate as margin, not just post-FEC zero errors. Run it hot, at supply corners, with neighboring interfaces active.