power switching fundamentals

MOSFET Switch Primer

High-side and low-side switching with NMOS and PMOS: how each is wired, what the gate has to do, where it breaks, and a fully worked LED driver. Every schematic marks G, D and S. Part values in the worked example are illustrative of common SOT-23 classes; check your actual datasheet.

01Terminals: gate, drain, source, body

Enhancement-mode symbols. The broken channel line means "off at V_GS = 0". The body arrow points in for N-channel and out for P-channel. The PMOS is drawn source-up, the way it sits in a high-side switch.

Gate (G) is an insulated plate. It draws no DC current, only the charge needed to charge its capacitance (Q_g, tens of nC on power parts). That charge is why gate drivers exist.
Source (S) is the reference. Everything that controls the device is measured from the source: V_GS = V_G − V_S. Grounding the gate turns a MOSFET off only if the source is also at ground.
Drain (D) is the terminal that blocks the supply voltage when off. V_DS(max) is the drain-to-source rating.
Body is tied to the source inside discrete MOSFETs. That tie forms the body diode between body and drain. It is always present, it conducts whenever the "wrong" terminal is more positive, and it decides which way round the part can be installed.

	NMOS	PMOS
Carriers	Electrons	Holes (≈ 2–3× lower mobility)
Turn-on condition	V_GS > +V_th (gate above source)	V_GS < −\|V_th\| (gate below source)
Normal current direction	Drain → source	Source → drain
Where the source sits in a switch	Most negative node (ground for low-side)	Most positive node (supply for high-side)
Body diode	Anode at S, cathode at D	Anode at D, cathode at S
R_DS(on) for the same die area	1×	≈ 2–3×; so for equal R_DS(on) a PMOS is bigger, has more Q_g, and costs more
Availability	Everything from 12 V to kV, mΩ-class	Good up to ~100 V; thin above that

Both conduct in either direction once the channel is on. The channel is just a resistor; the direction labels above are how the parts are normally used so the body diode blocks when the switch is off.

02The one rule that decides every topology

RulePut the source on the stiff rail and swing the gate away from it. NMOS: source at the most negative point, gate pulled up to turn on. PMOS: source at the most positive point, gate pulled down to turn on. Orient the body diode so it is reverse-biased when the switch is off.

The two "natural" switches follow directly: NMOS on the low side (source = ground, gate driven straight from logic) and PMOS on the high side (source = supply, gate pulled below the supply). The other two combinations put the source on the load node, which moves. A moving source means the gate drive has to move with it, which is the whole difficulty of NMOS high-side drive, and why PMOS low-side is almost never used.

A quick check for any schematic: find the source, ask what voltage it sits at when the switch is on, then add (NMOS) or subtract (PMOS) the V_GS the datasheet specifies R_DS(on) at. That is the gate voltage your driver must produce.

03The four topologies

Try each one live in the MOSFET Switch Simulator: ON/OFF buttons, adjustable supply and load, and drive options that reproduce each failure below.

A · NMOS low-side default choice

Wiring

S to ground. D to the bottom of the load. Load top to +V.
Gate from logic through R_G (10–220 Ω); R_PD (10–100 kΩ) G to S holds it off while the driver is high-impedance.

Gate

Off: V_G = 0. On: V_G = V_GS at which R_DS(on) is specified (2.5 V, 4.5 V or 10 V).
From a 3.3 V MCU, use a logic-level part with R_DS(on) guaranteed at 2.5 V. For big FETs, a low-side gate driver IC (2–4 A peak) at 10–12 V.

Strengths

Cheapest, lowest R_DS(on), simplest drive, no level shift. Easy current sense: a shunt between S and ground is ground-referenced.

Weaknesses

The load is not ground-referenced; it sits at +V when "off". A wire from the load to the FET shorting to chassis turns the load on and cannot be switched off.
Switching a load's ground breaks its reference. If the load has any other ground-referenced connection (a sensor with an I²C or analog line), current sneaks through that pin's ESD diodes.
Ground bounce: I·R of the power return shifts the source relative to the driver ground and eats V_GS. Use a Kelvin source connection for fast or high-current parts.

Used for

Indicator and illumination LEDs, solenoids, relays, fans, the low half of every bridge, automotive low-side drivers (LSDs).

B · PMOS high-side simple high side

Wiring

S to +V. D to the top of the load. Load bottom to ground.
R1 from G to S holds V_GS = 0 (off). Q2, a small NMOS, pulls the gate down through R2 to turn on.

Gate

Off: V_G = +V. On: V_G = +V − |V_GS(spec)|. The divider sets |V_GS| = V+·R2/(R1+R2), keeping it under V_GS(max) (±20 V, or ±8–12 V on logic-level parts). Above about 20 V supply, add a 10–12 V zener G–S as a clamp.
Direct drive from a GPIO works only if +V equals the logic supply. With +V = 12 V and a 3.3 V GPIO, "high" is V_GS = −8.7 V: always on, and the GPIO's ESD diode back-feeds.

Strengths

Load is ground-referenced and dead when off: a shorted harness wire downstream of an off switch is harmless.
No voltage above the supply needed; works at 100% duty.

Weaknesses

2–3× the R_DS(on) of an equal-size NMOS; more Q_g.
Resistor pull-up gives slow turn-off (tens of µs with 10 kΩ): fine for on/off and 1 kHz PWM, poor at 20 kHz+.
Body diode back-feeds the supply if the load side is driven above +V (back-driven motor, second supply). True disconnect needs two FETs source-to-source.

Used for

Load switches, sensor and peripheral power rails, reverse-battery protection (installed "backwards", see §7), rails up to ~60 V and a few amps.

C · NMOS high-side needs a driver

Wiring

D to +V. S to the top of the load. Load bottom to ground.
Gate driven by a floating driver referenced to the source (switch node).

Gate

When on, the source rises to ≈ +V. To stay enhanced, V_G must be +V + V_GS(spec), e.g. 12 V + 10 V = 22 V.
Bootstrap: a capacitor charged while the switch is off rides up with the source. Cheap, but needs regular off-time to recharge, so no 100% duty.
Charge pump: supports DC on. Used in smart high-side switches and many motor drivers.
Isolated supply or isolated driver: for high voltage, needs high CMTI (common-mode transient immunity) because the switch node slews 10–100 V/ns.

The trap

Drive the gate only to +V and the FET becomes a source follower: V_S = +V − V_GS(at that current), and it dissipates I·V_GS. At 5 A and 3 V that is 15 W in a part sized for 0.5 W.

Strengths

Lowest R_DS(on) for a high-side switch; the only practical choice at high current or high voltage.

Used for

The high half of every half-bridge (buck converters, motor inverters, GaN stages), automotive smart high-side switches (HSDs) and eFuses, which integrate the NMOS, charge pump, current limit, thermal shutdown and a current-sense output.

D · PMOS low-side rarely used

Wiring

The body diode must block when off, so the S goes to the more positive end, the bottom of the load. D goes to ground.

Gate

When on, the source is pulled toward ground. To stay enhanced, V_G must be below ground by |V_GS(spec)|, which needs a negative rail.
With the gate at 0 V it is a source follower: the source settles at |V_GS| above ground (2–4 V), the load loses that voltage and the FET dissipates it.

Why it exists

It combines the worst of both: P-channel R_DS(on) plus a floating-source drive problem. It appears only where a negative rail already exists (some audio and analog switching). It is a common interview question precisely because the answer is "don't, and here is why".

04Side-by-side

Topology	Source tied to	Gate off / on	Drive	Load ref.	Typical use
NMOS low-side	Ground	0 V / +2.5…10 V	Direct from logic	Floating at +V	LEDs, relays, solenoids, bridge low side
PMOS high-side	+V	+V / +V − 4.5…10 V	Level shift (small NMOS + divider)	Ground	Load switches, sensor rails, reverse-battery
NMOS high-side	Load (moves to +V)	V_S / +V + 5…10 V	Bootstrap, charge pump, isolated	Ground	Half-bridges, smart HSDs, eFuses, high current
PMOS low-side	Load (moves to 0 V)	V_S / below 0 V	Negative rail	Floating	Almost never

High-side or low-side: the decision

Question	Points to low-side	Points to high-side
Does the load have other ground-referenced connections?	No (LED, coil, heater)	Yes (sensor, module with comms)
Is the load at the end of a harness?	Short, inside an enclosure	Yes: a chassis short on an off high-side output is harmless
Should the load be dead when off (service, corrosion)?	Not needed	Yes; a low-side-off load still sits at +V, which drives electrochemical corrosion on wet connectors
Current and cost	High current, lowest cost	Pay for PMOS area or an NMOS driver
Current measurement	Ground-referenced shunt, simple amp	High-side shunt amp or the HSD's sense output
Safety-relevant loads (holding brakes, STO)	Switch both sides: a single short to ground or to supply cannot energize the load

05Reading the datasheet for a switch

Qualitative R_DS(on) vs V_GS. Near threshold the resistance is steep and part-to-part spread is large; past the spec point it flattens.

The V_GS(th) trapV_GS(th) is the gate voltage at which only 250 µA (sometimes 1 mA) flows. It is a turn-off limit, not a turn-on value, and it falls a few mV/°C, so a hot FET turns on more easily from noise. Design to the V_GS where R_DS(on) is guaranteed. A "2N7002 on a 3.3 V GPIO" has V_GS(th) up to 2.5 V and R_DS(on) specified at 5–10 V: it may work on the bench and fail on a cold, high-threshold unit.

Parameter	What it tells you	Switch design rule
V_DS(max)	Breakdown, drain to source	≥ 1.5–2× bus, plus inductive and transient overshoot. 12 V → 30 V; 24 V → 40–60 V; 48 V → 80–100 V. Automotive 12 V with load dump → 40 V+ or a clamp.
V_GS(max)	Gate oxide limit, typically ±20 V; ±8–12 V on logic-level parts	Never exceed, even transiently. Clamp with a zener when the drive could.
V_GS(th)	Threshold at 250 µA, min/max spread ≈ 1 V	Off-state margin: noise on the gate must stay below the minimum.
R_DS(on) @ V_GS	On-resistance at a stated V_GS and 25 °C	Use the value at your guaranteed V_GS; multiply by 1.4–1.8 for hot (positive tempco).
I_D	Often a thermal calculation at T_C = 25 °C, or package-limited	Ignore the headline. Compute I²·R_DS(on),hot and check temperature with your copper.
Q_g, Q_gs, Q_gd	Gate charge; Q_gd is the Miller charge	Sets driver current, switching time and gate-drive power.
C_iss, C_oss, C_rss	Input, output and reverse-transfer capacitance; all fall with V_DS	C_rss (= C_gd) couples dv/dt into the gate: false turn-on risk.
V_SD, t_rr, Q_rr	Body diode forward drop (~0.7–1.2 V) and recovery	Matters for freewheeling and dead time. GaN has no body diode and zero Q_rr but ~2–3 V reverse conduction.
R_θJA, R_θJC	Thermal resistance	R_θJA is for a specific test board; your board decides the real number. SOT-23 ≈ 100–250 °C/W.
SOA	Safe operating area, V_DS vs I_D vs time	Critical for linear operation, inrush and hot-swap. Modern trench parts have weak DC SOA.
E_AS	Single-pulse avalanche energy	Only for unclamped inductive turn-off; better to clamp than to rely on it.

06Switching dynamics and losses

Turn-on into a clamped or resistive load. Teal: V_GS. Amber: V_DS. Dashed: I_D.

0 → t0: gate charges C_iss up to V_th. Nothing happens at the drain (turn-on delay).
t0 → t1: current rises to the load current; V_DS is still high. Charge = Q_gs.
t1 → t2: Miller plateau. V_GS stays flat while the driver discharges C_gd as the drain falls. Charge = Q_gd. Most switching loss happens here.
t2 → t3: gate rises to the full drive voltage, R_DS(on) reaches its final value.

Gate current at plateau I_G ≈ (V_drive − V_plateau) / (R_G + R_driver) turn-on I_G ≈ V_plateau / (R_G + R_driver) turn-off (driver to 0 V) Transition time t ≈ Q_gd / I_G Switching loss P_sw ≈ ½ · V_DS · I_D · (t_r + t_f) · f_sw Output-capacitance loss P_oss ≈ ½ · C_oss · V² · f_sw (hard switching) Conduction loss P_cond = I_rms² · R_DS(on),hot Gate-drive power P_g = Q_g · V_drive · f_sw (dissipated in driver and R_G)

Gate resistor: what it trades

Smaller R_G: faster edges, lower switching loss, more ringing, more EMI, higher peak current from the driver (a GPIO is typically rated 8–20 mA).
Larger R_G: slower edges and more loss, but damps the gate loop L–C_iss resonance and lowers dv/dt into long harnesses.
Split turn-on and turn-off resistors (resistor + diode) when you want a soft turn-on and a hard turn-off, the usual choice against dv/dt-induced false turn-on in bridges.
The G–S pull-down holds the device off when the driver is high-impedance (MCU reset, boot, brown-out). Without it, drain dv/dt through C_gd can lift a floating gate past threshold and leave the FET half-on and hot.

Temperature behaviour

R_DS(on) rises with temperature (about 1.5–1.8× from 25 °C to 150 °C). In a fully enhanced switch that is self-balancing, which is why paralleled MOSFETs share current. Near threshold, in linear operation, the threshold's negative tempco dominates: hot spots conduct more and can run away. That is why linear-mode use (current sinks, inrush limiting) needs a check against the DC SOA curve, not just R_θ.

07Faults, inductive loads and protection

Inductive load, low-side

At turn-off the coil keeps its current and drives the drain above +V until something conducts. Put a freewheel diode across the load (cathode to +V). The drain is clamped to +V + V_F. Decay is slow (relays drop out late); for fast decay use a zener in series with the diode, or an active clamp (zener from drain to gate) and size the FET for the energy ½LI².

Inductive load, high-side

At turn-off the load node swings negative. Freewheel diode from ground (anode) to the load node (cathode). Smart HSDs instead clamp internally at roughly V_bat minus 40–50 V for fast demagnetization; check that energy against their E_AS spec.

Reverse-battery PMOS

A PMOS in the supply line with D toward the battery, S toward the load and G to ground through a resistor, with a zener G–S. Correct polarity: the body diode conducts first, lifts the source, V_GS goes negative and the channel shorts the diode. Reverse polarity: the diode blocks and V_GS ≈ 0, so it stays off. An NMOS in the ground return (S to battery −, G to +V) does the same with lower loss.

Back-feed through the body diode

An "off" PMOS high-side switch conducts from drain to source through its diode if the load side is higher than +V. To isolate both ways, use two MOSFETs source-to-source with a common gate (the ideal-diode and load-switch controller topology).

Short to ground / short to supply

Low-side: a short of the load-to-drain wire to chassis turns the load on uncontrollably; a short of +V to chassis is a supply fault. High-side: a short of the output to chassis is an overcurrent the switch can detect and limit. A short to supply on a high-side output back-powers the load; diagnose it by measuring the output while off.

Smart switches (HSD / LSD / eFuse)

Integrated NMOS + charge pump + current limit + thermal shutdown + diagnostics (current-sense output proportional to load current, open-load detection in off state). This is the automotive answer for most body loads, and the basis of the eFuse and HSD/LSD work on the GM aggregator.

Gate protection checklist

Zener or TVS from G to S whenever the drive source could exceed V_GS(max) (high-side divider on a rail that varies, long gate traces near switching nodes).
Series R_G limits ESD and fault current into the driver pin.
TVS at the drain for harness-connected loads: ESD and inductive kick from the wire itself.
Keep the gate loop (driver → G → S → driver return) small and Kelvin-connected; its inductance with C_iss rings.

08Worked example: switching an LED string

Task. Drive three white LEDs in series at 100 mA from a 12 V rail (±5%), dimmable by PWM from a 3.3 V MCU GPIO. Design it low-side (Option A), then high-side (Option B), compare, and then fix the current accuracy with a constant-current sink (Option C).

Given	Value	Notes
Supply V+	12 V ± 5% (11.4–12.6 V)	Regulated rail. A raw automotive 12 V (9–16 V, load dump) would change the answer: use Option C or a dedicated driver.
LED	V_F 3.0 V typ (2.8–3.2 V) @ 100 mA	Illustrative mid-power white LED. Abs-max ≈ 150 mA. V_F falls ≈ 2–4 mV/°C as it heats.
LED count	3 in series	String V_F: 9.0 V typ, 8.4–9.6 V
Target current	100 mA
GPIO	3.3 V, V_OH ≥ 2.9 V at 8 mA	Recommended ≤ 8–12 mA per pin; high-impedance during reset.

Option A · NMOS low-side

Current path: +12 V → R_S → D1 → D2 → D3 → Q1 drain → Q1 source → ground. Q1: G from the GPIO through 220 Ω, S to ground, D to the cathode of D3.

Why low-side here. An LED string has no other ground connection, so switching its return is harmless. The gate drive is referenced to ground, so the 3.3 V GPIO drives it directly. Cheapest and simplest.

Series resistor. Headroom left for R_S is supply minus string minus the FET's drop.

V_FET = I · R_DS(on) = 0.1 A × 0.05 Ω = 5 mV (negligible) R_S = (V+ − n·V_F − V_FET) / I = (12 − 9.0 − 0.005) / 0.1 = 29.95 Ω → 30 Ω (E24) I_nom = (12 − 9.0) / 30 = 100 mA

Corner analysis. With only 3 V of headroom, small supply and V_F errors become large current errors.

Corner	V+	String V_F	Headroom	I_LED	P(R_S)
Minimum	11.4 V	9.6 V	1.8 V	60 mA	0.11 W
Nominal	12.0 V	9.0 V	3.0 V	100 mA	0.30 W
Maximum	12.6 V	8.4 V	4.2 V	140 mA	0.59 W

Current spread is −40% / +40%. 140 mA stays under the 150 mA abs-max, but only just; brightness varies visibly between units. Two LEDs with 60 Ω would give 83–117 mA (±17%) at 50% efficiency instead of 75%. The real fix is constant current (Option C). For the exercise we proceed with 30 Ω.

Resistor rating. Worst case 0.59 W. With 50% derating, use a 1 W part (2512), or two 15 Ω 1206 parts in series (0.29 W each, which also spreads the heat).

Pick Q1. Illustrative 30 V logic-level NMOS in SOT-23 (AO3400A class):

Spec	Value	Check
V_DS(max)	30 V	2.4× the 12.6 V max rail ✓
V_GS(max)	±12 V	Drive is 3.3 V ✓
V_GS(th)	0.65–1.45 V	Max 1.45 V ≪ 2.9 V worst-case drive ✓; min 0.65 V vs off-state gate ≈ 0 V ✓
R_DS(on) @ 2.5 V	≤ 52 mΩ	Guaranteed below our 2.9 V minimum drive ✓
Q_g / Q_gd	≈ 4 nC @ 3.3 V / ≈ 1.5 nC	Used in step 7
R_θJA	≈ 125 °C/W	Used in step 8

Why not a 2N7002: V_GS(th) up to 2.5 V and R_DS(on) up to several ohms specified at 5–10 V. At 2.9 V drive a high-threshold unit may barely conduct. It would "work on the bench".

Gate network.

R_PD = 100 kΩ G to S (placed at the gate, after R_G): holds Q1 off while the GPIO is high-impedance during reset and boot. Static load on the GPIO when high: 3.3 V / 100 kΩ = 33 µA. Divider loss on V_GS: 3.3 × 100k / 100.22k ≈ 3.29 V.
R_G = 220 Ω: limits peak GPIO current. With ≈ 40 Ω GPIO output resistance, R_total ≈ 260 Ω; peak = 3.3 / 260 = 12.7 mA, within the pin rating. (100 Ω would give ≈ 24 mA peak, too much for many MCUs.) It also isolates the GPIO from ESD and from drain dv/dt coupled through C_gd.

PWM frequency and switching. Choose 20 kHz: above audible (no ceramic-capacitor singing) and far above flicker. On a robot with cameras, low PWM frequencies alias with exposure time and show as banding; 20 kHz or synchronizing PWM to the camera avoids it.

Plateau ≈ 1.5 V at 100 mA Turn-on I_G = (3.3 − 1.5) / 260 Ω = 6.9 mA → t_r ≈ 1.5 nC / 6.9 mA = 0.22 µs Turn-off I_G = 1.5 / 260 Ω = 5.8 mA → t_f ≈ 1.5 nC / 5.8 mA = 0.26 µs P_sw ≤ ½ · 12 V · 0.1 A · (0.22 + 0.26) µs · 20 kHz = 5.7 mW (upper bound: assumes full 12 V swing) P_g = Q_g · V · f = 4 nC · 3.3 V · 20 kHz = 0.26 mW (avg GPIO current = Q_g·f = 80 µA)

Dimming resolution: edges take ~0.5 µs of a 50 µs period, so duty below ~2% is not clean. A 64 MHz timer gives 3,200 counts per period (≈ 11.6 bits), more than the edges can use. If you need deep dimming, drop to 1–2 kHz or add analog dimming.

Q1 thermal.

R_DS(on),hot ≈ 52 mΩ × 1.4 = 73 mΩ P_cond = I² · R · D = (0.1)² × 0.073 × 1.0 = 0.73 mW (100% duty, worst case 1.4 mW at 140 mA) P_total ≈ 0.73 + 5.7 + ~0 ≈ 6.5 mW ΔT_J = 6.5 mW × 125 °C/W ≈ 0.8 °C

Q1 is loafing. The heat in this circuit is in R_S (0.3 W) and the LEDs (0.9 W).

Off-state and faults. When off, the drain floats up toward 12 V through the LEDs' leakage, which is under Q1's 30 V rating. If the wire from D3 to the drain is on a harness and shorts to chassis, the LEDs turn on at 100 mA, still limited by R_S: annoying, not dangerous. If the LED module is remote, add a TVS at the drain for ESD.

Option B · PMOS high-side with level shifter

Q1 PMOS: S to +12 V, D to R_S, G to the R1/R2 node. Q2 small NMOS: D to R2, S to ground, G from the GPIO. The LED string is ground-referenced.

Why you might want it. The LED module is remote (on an arm, a panel or an indicator light). With high-side switching the harness is dead when off, and a chassis short on the output is an overcurrent you can detect rather than an LED stuck on.

Same series resistor: 30 Ω, same corner spread. Only the switch moved.

Gate divider. R1 = R2 = 10 kΩ.

Off: Q2 off → R1 pulls G to +V → V_GS = 0 On: Q2 on → V_G = V+ · R2/(R1+R2) = 6 V → V_GS = −6.0 V (−5.7 V at 11.4 V, −6.3 V at 12.6 V) Divider current when on: 12 V / 20 kΩ = 0.6 mA → 7.2 mW × duty

Check against an illustrative −30 V PMOS (AO3401A class): R_DS(on) specified at −4.5 V (≈ 60 mΩ) ✓, |V_GS| 6.3 V ≪ V_GS(max) ✓. On a 24 V rail the same divider would put −12 V on the gate, at the limit of a ±12 V part: change the ratio or add a zener.

Q2 selection. It sinks 0.6 mA, so R_DS(on) barely matters, but it must turn on from 2.9 V. Pick a part with V_GS(th) max ≤ 1.5 V (BSS138 class, 0.8–1.5 V). 100 Ω series and 100 kΩ pull-down keep it off during MCU reset, which keeps Q1 off too.

Speed: the cost of resistor drive.

Q1 Q_gd ≈ 2 nC, plateau |V_GS| ≈ 2 V Turn-on (Thevenin 6 V via R1‖R2 = 5 kΩ): I_G = (6 − 2)/5 kΩ = 0.8 mA → 2.5 µs on the plateau Turn-off (via R1 = 10 kΩ only): I_G = 2 V/10 kΩ = 0.2 mA → 10 µs on the plateau Plus C_iss charging time constants (≈ 3 µs and 6 µs) → ~5 µs on, ~20 µs off in total

At 20 kHz the 50 µs period is mostly transition: unusable. At 1 kHz:

P_sw ≈ ½ · 12 V · 0.1 A · (2.5 + 10) µs · 1 kHz = 7.5 mW (plateau-only estimate)

Acceptable, but the LED then flickers on camera. To go faster: R1 = R2 = 1 kΩ (10× faster, 72 mW static divider loss), a complementary NPN/PNP emitter-follower referenced to +V, or a high-side load switch / driver IC.

Q1 losses. R_DS(on),hot ≈ 60 mΩ × 1.4 = 84 mΩ → 0.84 mW conduction; ~8 mW switching at 1 kHz. Still a few °C in SOT-23.

A vs B

	A · NMOS low-side	B · PMOS high-side
Parts	Q1, R_G, R_PD	Q1, Q2, R1, R2, 100 Ω, 100 kΩ
Practical PWM	20 kHz+	≈ 1 kHz with 10 kΩ divider
Static drive loss	33 µA from GPIO	0.6 mA from 12 V (7.2 mW)
Load when off	Floats near +12 V	0 V (dead)
Output wire short to chassis	LED stuck on	Overcurrent while on; harmless while off
Best for	On-board indicators and backlights	Remote or harness-connected lamps

Option C · constant-current sink (fixing the ±40%)

Q1 NMOS in its linear region: D to D3 cathode, S to R_SENSE, G from the op-amp output through R_G. The op-amp drives the gate until V(R_SENSE) = V_SET.

Current set point. I = V_SET / R_SENSE = 0.1 V / 1 Ω = 100 mA, independent of supply and V_F. Sense power: 0.1² × 1 = 10 mW. Accuracy ≈ R_SENSE 1% + V_SET 1% + op-amp offset (1 mV / 100 mV = 1%) ≈ ±3%, versus ±40% before.

Q1 now dissipates what R_S used to.

V_DS = V+ − n·V_F − V_SET Nominal 12.0 − 9.0 − 0.1 = 2.9 V → P = 0.29 W Maximum 12.6 − 8.4 − 0.1 = 4.1 V → P = 0.41 W Minimum 11.4 − 9.6 − 0.1 = 1.7 V → still regulating (needs only I·R_DS(on) + margin)

In SOT-23 (125 °C/W) that is +51 °C, too hot at 85 °C ambient. Use SOT-223 or DPAK on a copper pour (≈ 40–60 °C/W → +16 to +25 °C). Check the DC SOA line at 4.1 V / 0.1 A: this is linear operation, where trench FETs are weakest.

Op-amp and stability. Inputs must include ground (rail-to-rail input or ground-sensing); the output must reach V_th + a bit (≈ 2 V). The op-amp is driving a capacitive load (C_iss), so add R_G of 100 Ω–1 kΩ and, if needed, a small capacitor from output to the inverting input for compensation. Dim by scaling V_SET (analog) or by gating V_SET on and off (PWM at constant peak current).

Scaling it upOn a 48 V robot bus a resistor or linear sink would burn (48 − 9) × 0.1 ≈ 3.9 W for 0.9 W of light. That is where a buck LED driver (switching, constant current, ≈ 90% efficient) takes over. The switching element inside it is Topology C: an NMOS high-side with bootstrap drive.

Validation checklist for any of the three

Scope V_GS at the FET pins (not at the MCU) with a short ground spring: confirm the on level meets the R_DS(on) spec point and the off level is ≈ 0.
Power-up and MCU reset: the LED stays dark while the GPIO is high-impedance (the pull-down works).
Measure LED current at supply min/max and at hot and cold: compare against the corner table.
Thermal camera on R_S or the linear FET at max supply after 30 minutes.
Edges on the harness: ringing, conducted and radiated emissions; slow the gate if needed.
Fault injection: short the output to chassis and to +12 V with the switch on and off; confirm nothing exceeds ratings.
Camera check: film the LED with the robot's own cameras at their exposure settings; no banding.

09Series-resistor calculator

For the resistor-ballast versions (A and B). Change the inputs to see how headroom drives the current spread.

Supply V+ (V) Supply tolerance (±%) LEDs in series V_F typ (V) V_F spread (±V) Target I (mA) R_DS(on) (mΩ)

R exact–

Nearest E24–

I min / max–

Spread–

P(R) nom / max–

Efficiency (LED / total)–

10Interview drill

Why is NMOS low-side the default switch?

The source sits at ground, so V_GS equals the logic output: no level shift, no floating supply. NMOS also has 2–3× lower R_DS(on) per area than PMOS. The cost is that the load floats at +V when off and its ground is switched.

What happens if you drive an NMOS high-side gate only up to the supply?

It becomes a source follower. The source settles at V+ − V_GS at the load current, so the load loses several volts and the FET dissipates I·V_GS: 5 A × 3 V = 15 W. The gate needs V+ + 5–10 V, from a bootstrap, a charge pump or an isolated driver.

A 3.3 V GPIO drives a PMOS high-side switch on a 12 V rail directly. What happens?

GPIO high is 3.3 V, so V_GS = 3.3 − 12 = −8.7 V: on. GPIO low gives −12 V: also on, and at the limit of a ±12 V part. It can never turn off. Adding a pull-up to 12 V doesn't help: the GPIO's ESD diode clamps the gate at ≈ 3.9 V and back-feeds the MCU rail through the pull-up. Fix: a small NMOS or NPN level shifter with a divider (Option B in §8).

Why can't you install a MOSFET either way round as a switch?

The body diode. NMOS: anode at S, cathode at D. If D is below S, the diode conducts and the switch can't turn off. The exception is deliberate: reverse-polarity protection installs the FET "backwards" so the diode conducts first and the channel then bypasses it.

You low-side switch a sensor that also has an I²C line to the MCU. What goes wrong?

With its ground open, the sensor's internal ground floats up toward its supply. Current then finds a path out through the I²C pins' ESD diodes into the MCU's pull-ups and I/O, partially powering the part, corrupting the bus and stressing both chips. Switch such loads high-side, or use a load switch on the supply.

High-side or low-side for a harness-connected load, and why?

High-side. When off, the harness is at 0 V, so a chafed wire touching chassis does nothing and connectors aren't biased for corrosion. When on, a short is an overcurrent the switch can detect and limit. With low-side, a short from the switched wire to chassis turns the load on and you can't turn it off.

Is V_GS(th) a design value?

No. It is where only 250 µA flows, with about 1 V of spread and a negative tempco. It defines the off-state noise margin. Design the on-state to the V_GS where R_DS(on) is guaranteed.

How do you choose the gate resistor?

From three limits: peak driver current (V_drive/R_total within the pin or driver rating), switching time (t ≈ Q_gd/I_G, which sets switching loss and EMI), and damping of the gate loop's L–C ringing. Then split turn-on and turn-off resistors if dv/dt false turn-on is a risk.

Can you parallel MOSFETs?

Yes, as fully enhanced switches: R_DS(on) rises with temperature, so a hotter device carries less current. Give each its own gate resistor to stop oscillation between them and lay them out symmetrically. In linear mode it does not self-balance, because the threshold's negative tempco dominates; use source resistors or one bigger part.

Where does the energy go when you turn off a solenoid on a low-side switch with no diode?

The coil drives the drain up until the FET avalanches; ½LI² is dumped in the FET. Fine if the energy is within E_AS and repetitive ratings, otherwise it fails short. Use a freewheel diode (slow decay) or a zener / active clamp (fast decay, energy in the clamp or FET by design).

When would anyone use a PMOS low-side switch?

Almost never. It needs a gate voltage below ground to turn fully on and it has P-channel R_DS(on). Without a negative rail it acts as a source follower and wastes |V_GS|·I.

Why are both sides of a holding brake switched on a robot joint?

A single fault (a short to supply on the low side or to ground on the high side) can't energize the brake coil and release the joint. Two independent switches, one per side, each driven by separate channels, is the usual Cat 3 structure and lets each be tested for stuck-on.

11Cheat sheet

V_GS is measured from the source. Find the source's voltage when on before designing the gate drive.
NMOS: source low, gate up. PMOS: source high, gate down.
Body diode: NMOS S→D, PMOS D→S (anode → cathode). It decides orientation.
Natural pairs: NMOS low-side, PMOS high-side. NMOS high-side needs gate above the rail. PMOS low-side: don't.
Design to R_DS(on) at your guaranteed V_GS, never to V_GS(th).
Pull-down (or pull-up for PMOS) G–S always; the driver will be high-impedance at some point.
t ≈ Q_gd / I_G; P_sw ≈ ½VI(t_r+t_f)f; P_g = Q_gVf; P_cond = I²R_hot.
Harness loads, sensors with comms, safety loads → high-side (or both sides). On-board LEDs and coils → low-side.
Resistor ballast with little headroom gives poor current accuracy (±40% in the example); use constant current.