First Principles Primer

Everyone claims to be a first-principles thinker. In engineering it has a concrete meaning: you can get to a defensible number from conservation laws and a few material properties, without a datasheet curve or a past design to copy. Interviewers test it by asking for an estimate and watching how you get there.

The method

1. Name the quantity. Turn the question into a physical quantity with units: temperature rise in K, voltage drop in mV, torque in N·m.
2. Pick the conservation law. Charge (KCL), energy (KVL, power balance, heat balance), momentum (F = ma).
3. Add the constitutive relation. The material or component law that links effort to flow: V = IR, q = ΔT/Rθ, σ = Eε, τ = Kt·I.
4. Put in round numbers and compute to one significant figure first.
5. Check units and limits. Does the answer go the right way when you double an input? Does it reach a sensible value at zero or infinity?
6. Find the dominant term and say what would change the answer.

Example: why a 48 V bus?

For the same power P, current is I = P/V. Conduction loss is I²R = (P/V)²·R. Going from 12 V to 48 V cuts current to ¼ and loss to 1/16 for the same copper. 48 V also stays under the 60 V DC limit for safety extra-low voltage. Above that, touch-safety requirements get much harder.

Say it this wayFirst principles for me means: name the quantity, pick the conservation law, add the constitutive relation, get a one-digit number, check units and limits, then say which term dominates.

Ohm's law: V = I·R

It comes from the material: current density J = σE. For a conductor of length L and cross-section A, R = ρL/A.

Copper ρ = 1.72×10⁻⁸ Ω·m. 1 oz copper is 35 µm thick, so sheet resistance = ρ/t ≈ 0.49 mΩ per square.
A 0.25 mm × 50 mm trace = 200 squares → ≈ 98 mΩ. At 2 A that is 0.2 V and 0.4 W.

KCL: currents into a node sum to zero

It is conservation of charge: a node can't store charge (unless you draw a capacitor). Use it for current budgets, return paths and nodal analysis.

KVL: voltages around a loop sum to zero

It is conservation of energy in a conservative electric field. It holds exactly only if no changing magnetic flux passes through the loop. With changing flux, Faraday's law adds −dΦ/dt. That term is what you call loop inductance, and it is why layout matters:

v = L·di/dt. A 1 nH power loop with 20 A switched in 2 ns gives 1 nH × 20 A / 2 ns = 10 V of overshoot.

Capacitors and inductors

• Capacitor: i = C·dv/dt. Stored energy ½CV². Holds voltage, so it supplies short current bursts: ΔV = I·Δt/C. A 5 A step for 1 µs on 100 µF droops 50 mV.
• Inductor: v = L·di/dt. Stored energy ½LI². Holds current, so it fights fast current changes.
• Time constants: RC and L/R. After about 5τ the transient is within 1% of final.

Tools that follow from these

• Nodal analysis: KCL at each node with Ohm's law for branch currents.
• Superposition: in a linear circuit, solve one source at a time and add.
• Thevenin/Norton: any linear two-terminal network looks like a source plus an impedance. That is how you reason about loading, source impedance and power delivery.
• Power: P = V·I. Conduction loss I²R; switching loss ≈ ½·V·I·(t_r + t_f)·f_sw. At 48 V, 20 A, 4 ns total transition and 100 kHz, that is ≈ 0.19 W.

Say it this wayKCL is charge conservation and KVL is energy conservation. KVL breaks when changing flux threads the loop, and that correction is loop inductance: 1 nH at 10 A per ns is 10 V. That is why I care about loop area.

• Knee frequency: f ≈ 0.35 / t_rise. A 100 ps edge has content to about 3.5 GHz, whatever the clock rate.
• Propagation: v = c/√εr. In FR-4 with εr ≈ 4, v ≈ 1.5×10⁸ m/s, about 6.7 ps per mm.
• Lumped or transmission line: if the trace delay is more than about a sixth of the rise time, treat it as a transmission line, with characteristic impedance Z₀ = √(L/C), termination and reflections Γ = (Z_L − Z₀)/(Z_L + Z₀).
• Return current flows under the trace at high frequency because that path has the least inductance. Gaps in the reference plane force a detour, which adds inductance and radiates.
• Skin depth: δ = √(ρ / (π f μ)). In copper at 100 MHz, δ ≈ 6.6 µm, so a 35 µm trace uses only its surface at high frequency.

Say it this wayA 100 ps edge has energy to 3.5 GHz. At about 6.7 ps per millimetre in FR-4, anything longer than a few millimetres is a transmission line, so I think about impedance, termination and the return path.

Most physical systems you will meet are effort and flow with resistance and storage. Once you see the pattern, a thermal or mechanical problem becomes a circuit you already know how to solve.

The mapping shown is one consistent choice (mass as capacitance). The other common choice (force-voltage) maps mass to inductance. Either works if you stay consistent.

Say it this wayHeat flow is current, temperature is voltage, thermal resistance is resistance and thermal mass is capacitance. A heat-sink problem is an RC circuit, and the thermal time constant is Rθ times Cθ.

Kinematics

• Position x (or angle θ), velocity v = dx/dt, acceleration a = dv/dt, jerk = da/dt. Motion profiles limit jerk to reduce vibration.
• Rotational: ω = dθ/dt, α = dω/dt. Arc length s = r·θ, tip speed v = r·ω.

Dynamics

• Newton: F = m·a; rotational τ = J·α. Gravity torque about a joint: τ = m·g·r·cos(θ).
• Power: P = τ·ω. Energy: ½mv², ½Jω², m·g·h.
• Gearbox ratio N: torque ×N, speed ÷N, reflected inertia ÷N².

Motor as an electrical component

• Torque constant Kt (N·m/A) equals back-EMF constant Ke (V·s/rad) in SI units: τ = Kt·I and E = Ke·ω.
• Terminal voltage needed ≈ I·R + Ke·ω (plus L·di/dt during transients). Torque sets current and heat; speed sets voltage.
• Electrical time constant L/R sets how fast current can change, which is why the current loop runs fastest (10–40 kHz), then velocity, then position (about 1 kHz), each roughly 5–10× slower than the loop inside it.

Worked example: one shoulder joint

Holding a load costs power even with no motion (I²R). That is a heat and battery problem for a robot that holds parts for long periods, and a reason for brakes or non-back-drivable gearing.

Say it this wayTorque sets current, current sets heat by I²R, and speed sets back-EMF and so the voltage I need. A 2 kg load at half a metre is about 10 N·m at the joint, 2.5 A at the motor through a 100:1 gearbox, and about 3 W of copper loss just to hold it.

• Stress σ = F/A (Pa). Strain ε = ΔL/L (unitless). Hooke: σ = E·ε in the elastic range.
• Pressure p = F/A. A 10 N grip spread over a 1 cm² fingertip is 100 kPa. That sets the full-scale range of a tactile sensor.
• Strain gauges: ΔR/R = GF·ε, GF ≈ 2. 500 µε gives 0.1% resistance change, hence bridges and instrumentation amplifiers.
• Thermal expansion: ε = α·ΔT. Mismatched α between joined materials becomes stress every temperature cycle.
• Fatigue: repeated strain cycles crack solder and copper. Life falls steeply with strain amplitude (Coffin-Manson).
• Vibration: natural frequency f = (1/2π)·√(k/m). A 50 g part on a mount of stiffness 2×10⁵ N/m resonates near 320 Hz. Keep board and component resonances well above the excitation.

Worked examples

• Plated via barrel: FR-4 expands about 60 ppm/K through its thickness, copper 17. Over a 100 K swing the mismatch is 43×10⁻⁶ × 100 = 0.43% strain in the barrel. That is why thick boards and big thermal cycles crack vias.
• BGA corner joint: a 10 ppm/K mismatch between package and board, 80 K swing, 15 mm from the package centre: 10×10⁻⁶ × 80 × 15 mm = 12 µm of shear across a 0.3 mm joint ≈ 4% shear strain. Corners fail first; underfill spreads the load.
• Flex cable through a joint: bending strain ≈ t/(2R). A 0.1 mm flex bent to 1 mm radius sees 5%, far too much for repeated motion. Dynamic flex needs much larger radii and copper near the neutral axis.

Say it this wayThermal expansion mismatch turns temperature cycles into strain. 43 ppm/K over 100 K is 0.4% in a via barrel, and a BGA corner sees a few percent shear, which is why I care about underfill, board thickness and the thermal cycle profile.

• Conduction: Q̇ = k·A·ΔT/L, so Rθ = L/(k·A). Copper k ≈ 390 W/m·K, aluminium ≈ 200, FR-4 ≈ 0.3 through thickness, TIM ≈ 1–10.
• Convection: Q̇ = h·A·ΔT, Rθ = 1/(h·A). Natural air h ≈ 5–10 W/m²K; forced air ≈ 25–250; liquid much higher.
• Radiation: Q̇ = εσA(T⁴ − T∞⁴). Near room temperature it behaves like an extra h of about 5 W/m²K for a black surface.
• Thermal capacitance: Cθ = m·c_p. Time constant τ = Rθ·Cθ. A 2 kg aluminium chassis (c_p ≈ 900 J/kg·K) has 1,800 J/K; behind 0.3 K/W, τ ≈ 540 s.
• Junction temperature: T_j = T_ambient + P·Rθ. An LDO dissipating 1.5 W with θJA = 50 K/W at 25 °C ambient reaches 100 °C.

Board-level heat paths

One 0.3 mm via with 25 µm plating: copper area ≈ π(0.15² − 0.125²) mm² ≈ 0.022 mm².
Rθ = 1.6 mm ÷ (390 W/m·K × 0.022 mm²) ≈ 190 K/W per via. Twenty vias in parallel ≈ 9.5 K/W.

Power sources to estimate for the thermal engineer: conduction loss I²R (a 5 mΩ FET at 20 A is 2 W), switching loss ½·V·I·t·f, gate charge loss Qg·V·f, inductor and capacitor ESR losses, and regulator drop (V_in − V_out)·I.

Say it this wayHeat is current through thermal resistance. For 130 W into a 45 °C enclosure with an 80 °C plate limit I have 0.27 K/W total, which natural convection can't do without half a square metre of fins, so the module conducts into the chassis or a cold plate.

Thermal and electrical engineers use the same network math. Friction comes from mismatched assumptions, not physics. Agree on these early.

The process

1. Month one: a power budget and a one-dimensional resistance network, like the one above, to check feasibility.
2. CFD or FEA on the placed board and enclosure.
3. Prototype with thermocouples and IR imaging under the agreed load cases.
4. Correlate model to measurement, then iterate placement, copper and heat sinking.
5. Close the loop in firmware: thermistors, power modes and throttling before limits are reached.

Common mismatches

• Maximum power treated as continuous when the real workload is bursty, or the reverse.
• Room ambient used instead of the ambient inside a sealed enclosure.
• Heat flux (W/cm²) ignored: 10 W in a 3 mm package is very different from 10 W spread over a board.
• Board copper not modelled, so the board's heat spreading is missed.
• Late changes to the power map not communicated.

Your levers as the EE

Lower-loss parts (lower R_ds(on), higher-efficiency converters), placement near the heat exit path, copper pours and thermal vias, splitting hot parts apart, power modes, and sensor placement for closed-loop control.

The same habits apply to the mechanical engineer: stiffness and mounting, connector mating forces, vibration and shock specifications, tolerance stacks and keep-outs.

Say it this wayI give the thermal engineer a power map with operating cases and limits, they give me temperatures and the heat path. We share the same resistance-network language, so the useful work is agreeing on load cases and ambient early and correlating the model to IR and thermocouple data.