Field-Effect Transistors
Every major FET family: how each one conducts, how it turns on and off, where it wins and loses, and the questions interviewers use to probe whether you understand the device or just the symbol.
Family map and cross-sections
All FETs share one idea: a voltage on a gate modulates the conductivity of a channel between source and drain, and the gate draws (ideally) no DC current. They differ in how the gate couples to the channel and what the channel is made of.
Junction-gate
- JFET (Si, n/p-channel), depletion-mode only
- SiC JFET (power, normally-on, often cascoded)
- MESFET (Schottky gate, GaAs)
Insulated-gate (MOSFET / MISFET)
- Planar: enhancement / depletion, n / p, CMOS
- Power: VDMOS, trench (UMOS), superjunction, shielded-gate
- LDMOS (lateral, RF and integrated BCD)
- SiC MOSFET (planar, trench)
- 3D logic: FinFET, GAA nanosheet, FD-SOI, CFET
- TFT: a-Si, LTPS, IGZO
Heterostructure
- HEMT / pHEMT (GaAs/AlGaAs, InP), RF/mmWave
- GaN HEMT: d-mode, e-mode (p-GaN gate), cascode
Specialty / emerging
- Floating-gate and charge-trap (Flash memory)
- FeFET, NCFET, TFET (steep slope)
- ISFET / BioFET (sensors)
- Dual-gate MOSFET (RF mixer)
- CNTFET, 2D-material, organic FET
Device cross-sections
Pick a device. Drawings are schematic, not to scale; current flow is shown as electron motion.
- Conducts: through the bulk n channel between the two p+ gate junctions. Open at VGS=0.
- Turn off: more negative VGS widens both depletion regions until they meet (VGS=VP).
- Note: depletion is wider at the drain end because the reverse bias there is VDG, larger than VSG.
- Conducts: through a thin doped n layer; a Schottky barrier replaces the JFET's p-n gate.
- Turn off: negative VGS pushes the Schottky depletion down to the semi-insulating substrate.
- Limit: forward gate drive above ~0.7 V turns on the Schottky diode.
- Conducts: through a surface inversion layer only nanometres thick, induced by the gate field across the oxide.
- Turn on: VGS > Vth inverts p-type surface to n-type, bridging n+ source to n+ drain.
- Turn off: VGS → 0; the inversion layer disappears. Two back-to-back p-n junctions then block.
- Conducts: short lateral channel at the p-body surface, then vertically through the JFET neck and the n− drift.
- Blocks: the p-body / n− drift junction; drift thickness and doping set breakdown voltage.
- Body diode: that same p-body / n− drift junction, shorted to source by the metal.
- Conducts: vertical channels on both trench sidewalls; current goes straight down with no JFET neck.
- Why: much smaller cell pitch, so more channel width per mm² and lower RDS(on).
- Cost: gate faces the drift at the trench bottom, raising CGD; shielded-gate variants add a source-tied plate below the gate.
- Conducts: like VDMOS, down the n pillar, which can be doped ~10× heavier than a normal drift.
- Blocks: under high VDS the pillars deplete each other sideways (dashed), so the drift acts intrinsic and holds field evenly.
- Side effect: pillars fully deplete at a few tens of volts, so Coss collapses by orders of magnitude: very non-linear.
- Conducts: lateral channel in the p-body, then sideways along a lightly doped n drift to a top-side drain.
- Blocks: the drift length and the gate extension over thick field oxide (field plate) spread the field.
- Why: all terminals on top, so it integrates with CMOS logic (BCD) and has low source inductance for RF.
- Conducts: same trench geometry as Si, but the SiC/SiO₂ interface traps cut channel mobility, so strong +15 to +20 V gate drive is needed.
- Blocks: a thin, heavily doped drift holds ~10× the field of Si. That high field would reach the trench oxide corner, so a p+ shield (or a source-tied p+ region) screens it.
- Planar SiC (DMOS-like) avoids trench corners at the cost of larger cell pitch.
- Conducts: a 2D electron gas at the AlGaN/GaN interface, created by polarization charge, with no dopants in the channel.
- Turn on: +5 to +6 V on the p-GaN gate pulls the conduction band back down and restores the 2DEG under the gate.
- No body diode: there is no p-n junction from source to drain; reverse current flows through the channel itself. Without p-GaN (d-mode) the 2DEG is continuous and a negative gate turns it off.
- Conducts: electrons donated by dopants in the AlGaAs fall into the lower-bandgap InGaAs and travel there, away from ionized-impurity scattering (modulation doping).
- Turn off: negative VGS on the recessed Schottky gate depletes the 2DEG; e-mode pHEMTs use a deeper recess.
- "Pseudomorphic": InGaAs is strained to the GaAs lattice; kept thin to avoid dislocations.
- Conducts: MOS channel feeds electrons down; the p+ collector injects holes up. The drift floods with both carriers (conductivity modulation), so on-drop stays ~1.5–2 V even for thick drift.
- Turn off: the channel closes immediately, but stored holes must recombine or be swept out, which is the tail current.
- Compared to VDMOS: only the bottom layer changes, n+ → p+ (plus a field stop).
- Conducts: on the top and both sidewalls of each fin (accent outline), current flowing into the page.
- Why: the gate controls a thin fin from three sides, so the drain cannot reach under it; leakage and DIBL fall.
- Width comes in whole fins: drive strength is quantized, which constrains analog and SRAM sizing.
- Conducts: on all four faces of each stacked sheet.
- Why: full wrap gives the best electrostatics; sheet width is drawn in layout, so drive strength is continuous rather than per-fin.
- Made by: growing Si/SiGe superlattice, then selectively etching SiGe away and filling the gaps with high-k and metal.
- Conducts: through the whole thickness of an undoped Si film so thin that the gate depletes it entirely.
- Turn off: no deep body for the drain field to reach through, so leakage is low without heavy channel doping.
- Back bias: the BOX acts as a second gate dielectric; VBB shifts Vth by tens of mV per volt, tunable at run time.
- Conducts: an accumulation layer (not inversion) at the bottom of the semiconductor film, right against the gate insulator.
- No body terminal and no body diode; the film floats on glass.
- Material sets behavior: a-Si is slow and drifts under bias; LTPS is fast but non-uniform; IGZO leaks very little, enabling low refresh rates.
- Stores: electrons trapped on an isolated poly gate. Negative stored charge raises the Vth seen from the control gate.
- Program: high control-gate voltage (~15–20 V) tunnels electrons in (NAND) or channel hot electrons are injected (NOR). Erase: reverse the field.
- Read: apply a read voltage between the programmed and erased Vth and sense whether the cell conducts. Charge-trap flash replaces the poly with a nitride layer.
FET fundamentals
Vocabulary that applies to every FET
- Unipolar. Current is carried by majority carriers only (electrons in n-channel, holes in p-channel). No minority-carrier storage, so no storage time and no tail current. This is the root of the FET's switching-speed advantage over BJTs and IGBTs.
- Enhancement-mode (normally-off). No channel at VGS=0; gate voltage beyond threshold creates one.
- Depletion-mode (normally-on). Channel exists at VGS=0; gate voltage of the opposite polarity removes it. JFETs, MESFETs and native GaN HEMTs are depletion-mode.
- Threshold Vth / pinch-off VP. The gate voltage at which the channel just forms (MOSFET) or just closes (JFET). Datasheets define VGS(th) at a small drain current, often 250 µA or 1 mA. It is not the voltage at which the device is "on".
- Transconductance gm = ∂ID/∂VGS. Gain parameter. In power devices called gfs.
Operating regions (n-channel enhancement MOSFET)
| Region | Condition | Behavior | Used for |
|---|---|---|---|
| Cutoff / subthreshold | VGS < Vth | ID ≈ 0, falls exponentially with VGS | Off state, ultra-low-power analog |
| Triode / linear / ohmic | VGS > Vth, VDS < VGS−Vth | Voltage-controlled resistor | Power switch "on", load switch |
| Saturation (active) | VDS ≥ VGS−Vth | Channel pinched at drain; ID set by VGS | Amplifiers, current sources, linear regulators, inrush limiting |
Naming trap: MOSFET "saturation" is the BJT's active region, and MOSFET "linear/triode" corresponds to BJT saturation. Say which convention you mean.
See the MOSFET tab under Device cross-sections for the structure. Discrete parts tie body to source internally, which creates the body diode.
Core equations to be able to write from memory
JFET
A bar of n-type silicon (the channel) with p+ regions diffused on either side forming the gate. The gate-channel p-n junction is kept reverse-biased; its depletion region extends into the channel and narrows the conducting path.
Turn-on
It is already on. At VGS=0 the channel is fully open and the device carries IDSS in saturation. Maximum conduction is at VGS≈0; driving the gate forward beyond about +0.5 V forward-biases the junction and draws gate current, which defeats the purpose.
Turn-off
Drive VGS negative (n-channel) past the pinch-off voltage VP, typically −0.5 V to −8 V. The depletion regions from both sides meet and close the channel. A controller must therefore generate a negative rail, or the JFET must be cascoded.
Advantages
- Very low 1/f and voltage noise; classic for audio, instrumentation and photodiode front ends
- High input impedance (gate leakage pA–nA), no fragile oxide, robust to ESD
- Simple two-terminal current source (gate tied to source)
- Radiation tolerant, no oxide to trap charge
Disadvantages
- Normally-on: unsafe default for power stages if the driver loses supply
- Large part-to-part spread in IDSS and VP (often 3–5×)
- Gate leakage doubles roughly every 10 °C (it is a diode)
- Lower gm per area than MOSFETs; small-signal Si JFETs largely displaced by CMOS op-amps
MESFET
A JFET in which the gate junction is a metal-semiconductor (Schottky) contact instead of a p-n junction, built on GaAs or similar III-V material where a good gate oxide is not available. GaAs electron mobility (~8500 cm²/V·s bulk) is about six times silicon's, giving very high fT.
- On/off: identical to a JFET. Normally on; negative gate voltage depletes the thin doped channel. Schottky barrier limits forward gate drive to about +0.6–0.7 V.
- Strengths: microwave gain and low noise into tens of GHz; semi-insulating substrate keeps parasitics low.
- Weaknesses: limited gate swing, low breakdown, ionized-dopant scattering in the channel. Largely superseded by the pHEMT, which moves the electrons away from the dopants.
MOSFET
The gate is a capacitor plate separated from the semiconductor by a thin insulator. For an n-channel enhancement device on a p-body, positive VGS first repels holes (depletion), then, past threshold, attracts enough electrons to invert the surface into an n-type channel connecting n+ source and n+ drain.
The four flavors
| Type | Vth sign | Turn on | Turn off | Typical use |
|---|---|---|---|---|
| n-ch enhancement | + | VGS > Vth (e.g. 10 V std, 4.5 V logic-level) | VGS → 0 | Low-side switch, sync buck, almost all power |
| p-ch enhancement | − | VGS < Vth (gate pulled below source) | VGS → 0 (gate to source) | Simple high-side switch, reverse-polarity protection |
| n-ch depletion | − | On at VGS=0 | VGS < Vth (negative) | Start-up circuits, current limiters, constant-current sources |
| p-ch depletion | + | On at VGS=0 | VGS positive | Rare |
Why n-channel beats p-channel
Electron mobility in silicon is about 2–3× hole mobility, so a p-channel device needs 2–3× the die area for the same RDS(on), which also means 2–3× the gate charge. The p-channel advantage is drive simplicity on the high side: pull the gate to ground and it turns on, no bootstrap or charge pump.
Parasitics every MOSFET has
- Body diode. Source-body short plus body-drain junction. Conducts in third quadrant; in Si it has real reverse-recovery charge Qrr.
- Parasitic NPN. n+ source / p-body / n-drain. The source-body short suppresses it, but very high dv/dt or avalanche current through body resistance can turn it on and destroy the part (second breakdown).
- Capacitances. Ciss = CGS+CGD, Coss = CDS+CGD, Crss = CGD (Miller). All except CGS are strongly non-linear with VDS; that is why datasheets specify gate charge, not capacitance, for switching.
- Internal gate resistance RG(int). 0.5–5 Ω typical; sets a floor on switching speed and matters for paralleling.
CMOS in one paragraph
Complementary n and p devices in series between VDD and ground; one is always off in steady state, so static current is only leakage. Dynamic power is P = α·C·VDD²·f, plus short-circuit current during transitions. Latch-up is the parasitic PNPN thyristor formed by the wells; prevented with guard rings, well taps, and on advanced nodes SOI.
Power MOSFET structures
Power MOSFETs put the drain on the back of the die (vertical) so the blocking voltage is supported by a lightly doped drift region, and they parallel millions of cells. RDS(on) is a series stack: channel + JFET region + drift + substrate + package.
| Structure | How it works | Sweet spot | Trade-off |
|---|---|---|---|
| Planar VDMOS | Double-diffused body and source; horizontal channel at the surface, vertical current through drift. | Rugged, linear-mode SOA | JFET-region resistance, large cell pitch |
| Trench (UMOS) | Gate in an etched trench; vertical channel along trench wall; no JFET region. | 12–150 V, very low RDS(on) | Higher CGD, weaker linear-mode SOA |
| Shielded-gate trench (split-gate) | Field plate tied to source below the gate in the trench. | 25–250 V sync rectifiers, DC/DC | Very low QGD; more complex process |
| Superjunction | Alternating p and n pillars in the drift region; charge balance lets drift be heavily doped while still blocking. | 500–900 V PFC, flyback, LLC | Breaks the 2.5 power law (near-linear with BV); very non-linear Coss, harsh body-diode recovery |
| LDMOS | Lateral DMOS with drain extension; all terminals on top surface. | RF power amps to a few GHz; integrated BCD drivers, smart switches | Lower current density than vertical |
Turn-on and turn-off physics
A MOSFET switches by charging and discharging its gate capacitances. With an inductive load clamped by a freewheeling diode (the case in every buck converter or motor drive), the gate-charge curve has four intervals.
Inductive-load turn-on. Turn-off runs the same intervals in reverse: overdrive discharges, plateau while VDS rises, current falls, then VGS decays below Vth.
Turn-on, interval by interval
- td(on): charge Ciss to Vth. No drain current yet. Delay ≈ RG·Ciss·ln[Vdrv/(Vdrv−Vth)].
- ID rises. VGS keeps climbing; device is in saturation and takes current away from the freewheeling diode. VDS stays at the bus voltage because the diode is still conducting. Ends when ID = Iload at VGS = Vpl ≈ Vth + ID/gfs.
- Miller plateau. The diode turns off and VDS collapses. All gate current goes into discharging CGD, so VGS is pinned flat. dVDS/dt = IG/CGD with IG = (Vdrv−Vpl)/RG. This is where most switching loss happens.
- Overdrive. VGS rises to the drive rail, the channel fully enhances, RDS(on) drops to its datasheet value. Driving only to the plateau leaves the device in high resistance.
Turn-off
Gate discharges through RG(off). During the plateau, discharge current is Vpl/RG (into a 0 V rail) which is usually smaller than the turn-on current, so turn-off dv/dt is often slower unless you use a negative rail or a separate low-ohm turn-off path (diode across RG, or split source/sink driver outputs). Current falls only after VDS has risen to the bus and the freewheeling diode can take over; parasitic loop inductance then produces overshoot V = Lloop·di/dt.
Second-order effects interviewers like
- Miller-induced (parasitic) turn-on. When the other switch in a half-bridge turns on, dv/dt on this device's drain injects CGD·dv/dt into the gate. Divided by CGS and RG(off), it can lift VGS above Vth and cause shoot-through. Fixes: low-impedance off path, active Miller clamp, negative off bias, low CGD/CGS ratio.
- Common-source inductance. Source lead inductance shared by power and gate loops subtracts LS·di/dt from the gate drive, slowing switching and adding loss. Fix: Kelvin-source pin (4-pin TO-247, TOLL with sense pin).
- Dead time and body diode. In a synchronous buck the low-side body diode conducts during dead time; its Qrr is pulled through the high-side FET on the next turn-on, adding loss and ringing.
- ZVS. Soft-switching topologies (LLC, phase-shifted full bridge, ACF) discharge Coss with load current before turn-on, eliminating Eoss and Miller-plateau loss on turn-on.
SiC MOSFET and SiC JFET
4H-SiC has roughly 3× the bandgap and about 10× the critical field of silicon, so the drift region can be about 10× thinner and far more heavily doped for the same blocking voltage. Result: unipolar MOSFETs at 650–3300 V with resistance per area that silicon cannot reach, which is why SiC took over 800 V traction inverters and on-board chargers.
Turn-on
Typically +15 V to +20 V gate drive (device-specific; check datasheet). The SiC/SiO₂ interface has a high trap density and low channel mobility, so the channel needs strong overdrive to reach rated RDS(on). At +10 V a SiC MOSFET is far from fully on.
Turn-off
0 V works for some parts, but −3 V to −5 V is common. Vth is low (≈2–3 V at 25 °C) and drops at high temperature, and SiC switches with 50–100+ V/ns, so negative bias protects against Miller turn-on. Respect the negative VGS limit; exceeding it drifts Vth.
Advantages
- High voltage with low conduction loss, no tail current
- RDS(on) rises less with temperature than Si
- Thermal conductivity ~3× Si; junction ratings to 175–200 °C
- Body diode has very small Qrr vs Si superjunction
Disadvantages
- Body diode VF ≈ 3–4 V; keep dead time short or use synchronous rectification
- Gate oxide reliability and threshold drift (BTI) demand tight VGS control
- Bipolar degradation from basal-plane dislocations in older material
- Short-circuit withstand time ~2–3 µs vs ~10 µs for IGBTs; desat detection must be fast
- Cost, and EMI from high dv/dt
SiC JFET: no gate oxide, so no oxide reliability issue and very low RDS(on)·area. Normally-on, so usually sold as a cascode: a low-voltage Si MOSFET in series with the source, whose drain voltage drives the JFET gate negative. The pair behaves as a normally-off device driven by ordinary 0/12 V gate signals; the reverse-recovery is set by the LV MOSFET's body diode. Also used in solid-state circuit breakers because a normally-on device can carry current with the gate floating.
HEMT: GaN and GaAs
A High Electron Mobility Transistor forms its channel at the interface between two semiconductors of different bandgap. In AlGaN/GaN, spontaneous and piezoelectric polarization create a two-dimensional electron gas (2DEG) of ~10¹³ cm⁻² with no doping. Electrons travel in undoped GaN, so mobility is high (~1500–2000 cm²/V·s) and the channel is very conductive.
| GaN variant | Turn-on | Turn-off | Notes |
|---|---|---|---|
| Depletion-mode (native) | On at VGS=0 | VGS ≈ −5 to −10 V depletes the 2DEG | RF power amps (GaN-on-SiC); radar, 5G |
| E-mode, p-GaN gate | VGS ≈ +5 to +6 V (Vth ≈ 1.2–1.7 V) | 0 V, or −2 to −3 V for margin | Absolute max often +6/+7 V. Narrow window; dedicated drivers, tight layout |
| Cascode (d-mode GaN + LV Si MOSFET) | Si MOSFET gate 0/10–12 V | Si MOSFET off pulls GaN gate negative | Robust gate, standard drivers; Si diode adds small Qrr |
Advantages
- Very low QG and Qoss; MHz-class hard switching
- No body diode → zero Qrr; ideal for totem-pole PFC and hard-switched half-bridges
- Small die, chip-scale packages, low loop inductance
- Integrated drivers and half-bridges on one GaN die are common
Disadvantages
- Reverse conduction through the channel drops Vth+|VGS(off)| (2–4 V); dead time loss
- Dynamic RDS(on) / current collapse from trapped charge after high-voltage blocking
- No avalanche capability; overvoltage margin is the only protection
- Fragile gate; ringing of 1–2 V can exceed max VGS
- Mainstream ratings ≤650/700 V; higher-voltage parts are newer
GaAs / InP pHEMT: a pseudomorphic InGaAs channel with AlGaAs barrier, doping placed in the barrier (modulation doping) so electrons sit in undoped material. Lowest-noise LNAs and mmWave front ends (GNSS LNAs, satellite, automotive radar front ends historically). Low breakdown, so low power.
| Property (approx.) | Si | GaAs | 4H-SiC | GaN |
|---|---|---|---|---|
| Bandgap (eV) | 1.12 | 1.42 | 3.26 | 3.4 |
| Critical field (MV/cm) | 0.3 | 0.4 | ~2.5–3 | ~3.3 |
| Electron mobility (cm²/V·s) | 1400 | 8500 | ~900 bulk (channel far lower) | ~2000 (2DEG) |
| Thermal conductivity (W/cm·K) | 1.5 | 0.5 | ~3.7–4.9 | ~1.3–2.3 |
| Device orientation | Vertical & lateral | Lateral | Vertical | Lateral (GaN-on-Si) |
IGBT
Structurally a power MOSFET with an extra p+ layer on the drain side. The MOS channel supplies electrons that act as base current for a wide-base PNP; holes injected from the p+ collector flood the drift region (conductivity modulation), so on-state drop is roughly constant at VCE(sat) ≈ 1.3–2.5 V instead of I·R.
- Turn-on: same as a MOSFET gate (typically +15 V), Miller plateau included.
- Turn-off: the MOS channel closes instantly, but stored minority carriers in the drift region must recombine, producing a tail current at high VCE. Tail energy limits hard-switched frequency to roughly 20–50 kHz in practice.
- Versus MOSFET: wins at high current and high voltage where I·RDS(on) would exceed ~2 V; loses at light load (fixed knee voltage), at high frequency, and needs a co-packed antiparallel diode. Longer short-circuit withstand (~5–10 µs).
- Versus SiC MOSFET: SiC removes the knee voltage and the tail, giving better light-load efficiency (most of a vehicle's drive cycle) at higher device cost.
Logic FETs: FinFET, GAA, FD-SOI
As the channel shrinks, the drain's field reaches under the gate and lowers the source barrier (DIBL); Vth rolls off, subthreshold slope degrades and off-state leakage rises. Every modern architecture exists to give the gate more control over the channel than the drain has.
| Architecture | Gate wraps | Key idea | Notes |
|---|---|---|---|
| Planar bulk | 1 side | Doping and halo implants to fight short-channel effects | Random dopant fluctuation; ran out around 28/20 nm |
| FD-SOI | 1 side + back gate | Ultra-thin undoped body on buried oxide; body fully depleted | Back-bias tunes Vth at run time; good for RF, IoT, automotive MCUs |
| FinFET | 3 sides | Thin vertical fin; width quantized to integer fins | Mainstream from ~22/16 nm through ~3 nm |
| GAA / nanosheet | 4 sides | Stacked horizontal sheets fully wrapped by gate; sheet width tunable | Leading-edge nodes; often paired with backside power delivery |
| CFET | 4 sides, stacked n over p | Vertical stacking of nFET and pFET | Research / roadmap |
Gate stack history worth knowing: SiO₂ → high-k dielectric (HfO₂) + metal gate, introduced because sub-2 nm SiO₂ leaked by direct tunneling; strained silicon (SiGe in pMOS source/drain) boosts mobility.
TFT and specialty FETs
Thin-film transistor (TFT)
A MOSFET deposited on glass or plastic. Pixel switch and drive transistor in LCD and OLED backplanes, and the readout element in many touch and in-display fingerprint sensors.
- a-Si:H: cheap, uniform, μ ≈ 0.5–1; Vth shifts under bias stress
- LTPS: μ ≈ 50–100+, allows integrated gate drivers; grain-boundary non-uniformity needs OLED compensation circuits
- IGZO (oxide): μ ≈ 10–30, extremely low off-current → low refresh rates; LTPO combines LTPS and oxide
Floating-gate & charge-trap
A second, isolated gate (or a nitride trap layer) stores charge that shifts Vth. Program by hot-electron injection or Fowler-Nordheim tunneling; erase by tunneling. The basis of NAND/NOR Flash and EEPROM. Multi-level cells store 2–4 bits by placing Vth in 4–16 windows.
FeFET and NCFET
A ferroelectric (doped HfO₂) gate layer. FeFET: polarization state stores data non-volatilely. NCFET: negative-capacitance effect amplifies surface potential, a route to sub-60 mV/dec slope.
Tunnel FET (TFET)
p-i-n structure; gate controls band-to-band tunneling rather than thermionic emission over a barrier, so it is not bound by 60 mV/dec. Problem: on-current is low.
ISFET / BioFET
The gate metal is replaced by an electrolyte and reference electrode; ions or biomolecules on the sensing dielectric shift Vth. Used for pH sensing and semiconductor DNA sequencing.
Dual-gate, CNT, 2D, organic
Dual-gate MOSFET: two gates in series for RF mixers and AGC amplifiers with low feedback capacitance. CNTFET and 2D (MoS₂, WSe₂) channels promise atomically thin bodies; organic FETs give flexible, printable but slow circuits.
Master comparison
| Device | Default state | Gate type | Typical drive (on / off) | Voltage range | Reverse conduction | Strength | Weakness | Home application |
|---|---|---|---|---|---|---|---|---|
| Si JFET | On | p-n junction | 0 V / below VP | <50 V | Symmetric channel | Low noise, robust gate | Normally on, spread | Low-noise front ends, current sources |
| GaAs MESFET | On | Schottky | 0 V / negative | <20 V | Channel | Microwave gain | Small gate swing | Legacy RF |
| Si MOSFET (LV trench) | Off | Oxide | 4.5–10 V / 0 V | 12–250 V | Body diode (Qrr) | Lowest RDS(on), cheap | Qrr, SOA in linear mode | DC/DC, load switch, motor drive |
| Si superjunction | Off | Oxide | 10–12 V / 0 V | 500–900 V | Body diode (large Qrr) | Cheap HV switching | Non-linear Coss, Qrr | PFC, flyback, LLC |
| LDMOS | Off | Oxide | 5–10 V / 0 V | 20–100 V | Body diode | Integrable, RF linearity | Current density | RF PA, smart power ICs |
| SiC MOSFET | Off | Oxide | +15–20 V / 0 to −5 V | 650–3300 V | Body diode VF 3–4 V, low Qrr | HV, hot, low loss | Gate reliability, cost, short SC time | Traction inverter, OBC, DC fast charge |
| SiC JFET (cascode) | Off (pair) | p-n + Si MOSFET | 0–12 V / 0 V | 650–1700 V | Through LV MOSFET | Lowest R·A, no SiC oxide | Less dv/dt control | Solid-state breakers, PFC |
| GaN HEMT (e-mode) | Off | p-GaN | +5–6 V / 0 to −3 V | 15–700 V | Channel, ~2–4 V, zero Qrr | Speed, density | Gate margin, no avalanche | USB-PD adapters, 48 V DC/DC, lidar drivers |
| GaN HEMT (d-mode RF) | On | Schottky | −2 V bias / −5 to −10 V | 28–50 V supply | N/A | RF power density | Needs negative bias sequencing | Radar, base stations |
| GaAs pHEMT | On (mostly) | Schottky | bias near 0 V | <10 V | N/A | Lowest noise figure | Low power | LNAs, mmWave |
| IGBT (reference) | Off | Oxide | +15 V / 0 to −8 V | 600–6500 V | Co-pack diode | High current, robust SC | Tail current, knee voltage | Industrial drives, cost-sensitive traction |
Design pitfalls and datasheet reading
Temperature coefficients
RDS(on) has a positive tempco (Si: ~1.5–2× from 25 to 150 °C) because phonon scattering lowers mobility. Vth has a negative tempco (a few mV/°C). At high VGS the mobility term dominates, so current naturally balances among paralleled parts. Below the zero-temperature-coefficient (ZTC) point on the transfer curve, Vth wins: hot cells conduct more, leading to hotspots and thermal runaway (Spirito effect). This is why trench MOSFETs fail in linear-mode applications like hot-swap, eFuse soft-start and linear regulators even within the "DC SOA" line, and why parts with a guaranteed linear-mode SOA exist.
Paralleling
- Fine in the fully-enhanced state thanks to positive RDS(on) tempco
- During switching, Vth mismatch decides who switches first and takes the energy
- Use individual gate resistors to damp oscillation between devices
- Symmetric power and Kelvin-source layout
Avalanche and UIS
Si MOSFETs can absorb a single unclamped inductive spike (EAS) by avalanching the body diode. Repeated avalanche or high current density triggers the parasitic BJT. GaN has no avalanche mode; SiC has some. Prefer clamping (TVS, snubber) to relying on it.
Gate protection
- VGS(max) is usually ±20 V for Si, tighter for SiC (asymmetric) and GaN (+6/+7 V)
- Zener or TVS gate clamp; pull-down resistor (10–100 kΩ) so the gate cannot float during power-up
- Small RG or ferrite bead to kill gate ringing
Datasheet parameters to know cold
Continuous ID on page 1 assumes TC = 25 °C, an infinite heatsink. Real current capability comes from RDS(on) at hot Tj, Rθ to ambient and allowable rise.
Automotive and compute-board applications
| Function | Typical device | What matters |
|---|---|---|
| Multiphase VRM for SoC/GPU | LV trench Si in DrMOS / smart power stages; GaN emerging at 48 V | QGD, Qrr, RDS(on) of low side, integrated current sense, transient response |
| Reverse-battery protection | PMOS in high side, or NMOS with ideal-diode controller and charge pump | Body diode orientation, VGS clamp, back-to-back FETs for blocking both directions |
| eFuse / hot-swap / inrush limit | MOSFET with guaranteed linear-mode SOA | SOA at the dv/dt you set, Spirito effect, fault-timer energy |
| Load switch / power distribution | Smart high-side switches (integrated DMOS + charge pump + diagnostics) | Current sense, short-to-battery / open-load diagnostics, inductive clamp energy |
| 48 V ↔ 12 V DC/DC | 80–100 V Si trench or 100 V GaN | Switching frequency vs magnetics size, thermal path |
| Traction inverter, OBC | SiC MOSFET modules (800 V), IGBT at 400 V cost-sensitive | Short-circuit detection, gate driver isolation, dv/dt and EMI, sintered die attach |
| Radar / GNSS front ends | RF CMOS / SiGe for radar today; pHEMT LNAs in GNSS modules | Noise figure, linearity |
| Lidar laser driver | GaN FET | ns-scale current pulses, minimal loop inductance |
Driving an n-channel high-side switch needs a gate above the supply: bootstrap (cap charged when low side is on; cannot hold 100% duty without refresh) or charge pump (supports DC on). Qualification context: AEC-Q101 for discretes, plus mission-profile-based lifetime for SiC gate oxide.
Interview Q&A
Numbers given are representative ranges for orientation; always defend specific values from the datasheet of the part in question.