EtherCAT Primer

EtherCAT is an industrial Ethernet fieldbus that uses ordinary 100 Mb/s Ethernet hardware but runs it as a ring. The master sends one frame per cycle. That frame passes through every slave in turn, and each slave's EtherCAT Slave Controller (ESC) reads its outputs and writes its inputs into the frame while the bits are still passing through, in hardware, with well under a microsecond of delay per node. The last slave sends the frame back to the master on the return pair of the same cable. A separate mechanism, Distributed Clocks, synchronizes every slave's local clock to within well under a microsecond, so all joints act at the same instant even though the frame reached them at different times.

• Master: any standard Ethernet MAC plus a real-time software stack. No special silicon.
• Slave: a dedicated ESC chip (Beckhoff ET1100, Microchip LAN9252, TI Sitara PRU, FPGA IP core) between two PHYs and the local MCU.
• Physical layer: standard 100BASE-TX over Cat5e, two pairs, up to 100 m between nodes. The outbound frame uses one pair through every node; the return uses the other.
• Why robots use it: dozens of joints updated at 1–4 kHz with sub-microsecond synchronization, daisy-chained wiring, and a standard drive profile (CiA 402).

Say it this wayEtherCAT gives me one frame per cycle that every joint reads and writes on the fly, plus distributed clocks that align every joint to well under a microsecond. On the carrier board the master is just a standard Ethernet MAC and PHY; the determinism lives in the slave controllers and the protocol, not in special master hardware.

A robot needs every joint to receive a new setpoint and return its state every control cycle, with the same timing every time. Ordinary switched Ethernet cannot promise that:

• Store-and-forward switches receive a whole frame before sending it on. Each hop adds the full frame time plus queueing, and queueing varies with traffic.
• One frame per device is wasteful. A joint may need 10–20 bytes, but every Ethernet frame costs at least 64 bytes plus 20 bytes of preamble and gap. Forty joints means forty frames.
• Software stacks on each device add tens to hundreds of microseconds of variable delay.

EtherCAT keeps the Ethernet physical layer and frame format, so cables, connectors, magnetics and PHYs are commodity parts. It removes the switch, the per-device frame and the per-device software from the timing path.

Master side (your compute carrier board). The CPU runs the master stack and builds the cyclic frame in memory. The Ethernet MAC sends it by DMA over RGMII or MII to a 100BASE-TX PHY. The PHY drives the line through magnetics to an RJ45 or M12 D-coded connector. Nothing here is EtherCAT-specific; a standard NIC works.

Slave side (each joint module).

1. Port 0 in: connector, magnetics, then PHY port 0, which converts line symbols back to MII nibbles.
2. ESC: receives the frame on port 0, processes it on the fly, and passes it to port 1 almost immediately. If nothing is plugged into port 1, the ESC closes the loop internally and sends the frame back out of port 0.
3. Port 1 out: PHY port 1, magnetics and connector to the next slave.
4. SII EEPROM: holds the slave's identity and configuration (from its ESI XML description). The ESC loads it at power-up.
5. Shared 25 MHz clock: the ESC has no transmit FIFO when using MII, so the ESC and both PHYs must run from the same clock source.
6. PDI: the process data interface (SPI or a parallel host bus) lets the local MCU read outputs and write inputs in the ESC's RAM.
7. SYNC0: the distributed-clock unit raises this pulse at the synchronized instant. The MCU latches its setpoint and samples its encoder on SYNC0, not on frame arrival.
8. Motor drive: the MCU runs the CiA 402 drive state machine and the local current loop (FOC, PWM, encoder) at 10–40 kHz.

Say it this wayEach joint module is two PHYs, an ESC, an EEPROM and an MCU. The frame enters port 0, gets processed in hardware, leaves port 1, and comes back the same way on the return pair. The MCU acts on SYNC0, which is what makes the timing independent of where the joint sits in the chain.

EtherCAT normally runs on 100BASE-TX, the same physical layer as ordinary Fast Ethernet. Understanding it explains most board-level decisions.

How the bits get onto the cable

1. MII: the MAC or ESC hands the PHY 4 bits at a time on a 25 MHz clock. 4 × 25 MHz = 100 Mb/s.
2. 4B/5B: each 4-bit nibble becomes a 5-bit code chosen to guarantee enough transitions for clock recovery and to provide control symbols. Line rate becomes 5 × 25 MHz = 125 Mbaud.
3. Scrambling: the bit stream is XORed with a pseudo-random sequence so long repeated patterns do not concentrate energy at one frequency. This lowers EMI and keeps the signal balanced.
4. MLT-3: each 1 moves the line to the next of three levels (0, +1, 0, −1); each 0 holds. A full cycle needs four 1s, so the highest fundamental is 125/4 = 31.25 MHz. That is why 100 Mb/s fits on Cat5 cable rated to 100 MHz.
5. Pairs: one twisted pair transmits, the other receives (pins 1-2 and 3-6 on RJ45). Differential, 100 Ω, about 2 V peak to peak.
6. Magnetics: 1:1 transformers with common-mode chokes give galvanic isolation (1,500 V rms per IEEE 802.3), block common-mode noise, and remove DC. Center taps go to a Bob Smith termination (75 Ω per pair into a high-voltage capacitor to chassis).

Why EtherCAT forms a ring on a line of cable

Full-duplex Ethernet already has two independent directions in every cable. EtherCAT uses them as the two halves of a ring: the outbound frame travels on one pair from node to node, each ESC processing it as it passes; the return path uses the other pair, with each ESC simply forwarding. A line topology is therefore a logical ring with no extra cable.

PHY requirements for an ESC

Source: Beckhoff PHY Selection Guide v3.1. Example compliant 100BASE-TX PHYs listed there include Microchip KSZ8081 and KSZ8091, TI DP83826A and TLK110/111, and ADI ADIN1200.

Other physical variants

• EBUS: an LVDS-based physical layer used inside backplanes such as Beckhoff terminal stations. No PHY or magnetics, so lower delay and cost, but only for short internal links.
• EtherCAT P: carries two 24 V supplies (system and peripheral) on the same four wires as the data. Useful for reducing cable count to small modules.
• 100BASE-FX: fiber, for long runs or high-noise areas.
• EtherCAT G: 1 Gb/s variant using RGMII PHYs, for larger process images. Branches can fall back to 100 Mb/s.

Board design notes

• Route MII as a short, length-matched single-ended bus (25 MHz, so modest), referenced to ground, away from the motor power stage.
• Place magnetics close to the connector; keep the area between magnetics and connector free of other signals; tie the Bob Smith cap and connector shield to chassis, not to logic ground.
• Route MDI pairs as 100 Ω differential, matched within each pair, no stubs.
• TVS diodes on the line side for ESD and surge; the PHY should tolerate 4 kV ESD.
• Next to a motor inverter, treat the cable as an antenna: shielded cable, connector shield bonded to chassis at entry, and common-mode chokes.

Say it this wayIt's plain 100BASE-TX: 4B/5B to 125 Mbaud, scrambled, MLT-3 so the fundamental stays at 31 MHz, two pairs through magnetics. EtherCAT uses the two pairs as the two halves of a ring. The board-level rules come from latency: MII not RMII, a shared 25 MHz clock, PHYs under about 320 ns receive and 140 ns transmit, fast link-loss detection, and EEE off.

An EtherCAT frame is an ordinary Ethernet frame with EtherType 0x88A4. Inside are one or more datagrams, each with a command, an address, data and a working counter (WKC).

• Addressing modes: position (auto-increment, by place in the chain, used at start-up), configured station address (assigned by the master), broadcast, and logical. Logical addressing is what cyclic data uses.
• FMMU (fieldbus memory management unit): maps a range of the 4 GB logical address space onto local memory in each slave. The master sends one LRW (logical read-write) datagram covering every joint's data; each FMMU picks out its own slice.
• Working counter: every slave that successfully accesses its data increments it: a read adds 1, a write adds 2, a read-write adds 3. The master knows how many to expect. A wrong WKC means a slave missed its data that cycle.
• Processing on the fly: the ESC reads output bytes and inserts input bytes while the frame streams through. Only a few bits are buffered, so the per-node delay is the PHY RX and TX latency plus a small ESC delay, well under a microsecond in total.

Say it this wayThe cyclic data is one logical read-write datagram. Each slave's FMMU maps its slice, reads its setpoint and writes its feedback in transit, and bumps the working counter. If the WKC is wrong, the master knows a joint missed that cycle.

• Ports and loop control: up to four ports. An unconnected or failed port closes automatically and the frame turns around. That gives hot-connect, cable-break handling, and tree topologies through 3- and 4-port slaves.
• SyncManagers protect the shared RAM between the network and the local MCU. Mailbox mode is handshaked for acyclic messages. Buffered (three-buffer) mode for process data always gives both sides a consistent, latest copy without either side waiting.
• DPRAM: registers plus a few to tens of kilobytes of process data RAM.
• DC unit: the local 64-bit nanosecond clock, timestamping, SYNC0/SYNC1 outputs and LATCH inputs for timestamping external events such as an encoder index.
• Parts: Beckhoff ET1100 and ET1200 (external PHYs), Microchip LAN9252 and LAN925x (integrated PHYs, SPI or host bus), TI Sitara AM64x and AM243x (ESC in the PRU-ICSS alongside Arm cores), Infineon XMC4800, Renesas RZ/T2, and FPGA IP cores.

Without synchronization, joint 1 would act about 40 µs before joint 40, simply because the frame reaches it first, and the master's own send-time jitter would move every joint around cycle to cycle. Distributed clocks remove both effects.

1. The first DC-capable slave becomes the reference clock.
2. At start-up the master sends a broadcast that makes every port latch its local time as the frame passes, outbound and on return. From those timestamps it computes the propagation delay of every link.
3. It writes each slave's offset so every local clock reads the reference time.
4. Each cycle it reads the reference time and distributes it (an ARMW datagram). Each slave compares and nudges its clock rate, compensating crystal drift.
5. Each slave raises SYNC0 at a programmed system time. All joints latch setpoints and sample sensors at that instant.

The master's frame can now arrive with tens of microseconds of jitter and nothing changes, as long as it arrives before SYNC0. That is why a general-purpose OS on the master can be good enough, provided it meets the cycle deadline.

Say it this wayDistributed clocks measure every link's delay with timestamps on the way out and back, then steer each slave's clock to a reference. Joints act on SYNC0, not on frame arrival, so master jitter and position in the chain stop mattering.

• CoE (CANopen over EtherCAT): the CANopen object dictionary and SDO access over the mailbox. Most drives use it.
• CiA 402 drive profile: the standard servo state machine and modes. For robot joints the usual choices are cyclic synchronous position (CSP), velocity (CSV) or torque (CST), where the master sends a new setpoint every cycle and the drive interpolates.
• FoE: file access for firmware updates. EoE: tunnels ordinary Ethernet (for example a web page or diagnostics) through the mailbox. SoE: the SERCOS drive profile.
• FSoE (Safety over EtherCAT): a black-channel safety protocol for safe stop and safe torque off commands, rated up to SIL 3 under IEC 61784-3. Safety frames ride inside normal process data with their own CRCs and watchdogs, so the network itself does not need to be safety-rated.

Say it this wayDrives come up through Init, Pre-Op, Safe-Op, Op. Configuration is CoE in Pre-Op; cyclic control is CiA 402 cyclic synchronous torque or position. Safety commands ride as FSoE inside the same frames, using the black-channel principle.

Assumptions: 40 joint slaves in one line, each exchanging 12 bytes out (target torque, control word, offsets) and 12 bytes in (position, velocity, torque, status). One LRW datagram for all of them.

Data rate is 960 B × 1 kHz ≈ 1 MB/s each way, trivial next to the carrier board's camera traffic. The limit on cycle rate is the frame time and the master's ability to compute and send on time, not bandwidth. If 40 joints at 4 kHz is not enough, split into two EtherCAT segments on two master ports, or move to EtherCAT G.

The ETG's published reference points: about 1,000 distributed digital I/O in roughly 30 µs, and 100 servo axes in about 100 µs.

Say it this wayForty joints at 24 bytes each is under a kilobyte, about 81 µs on the wire plus about a microsecond per node, so roughly 120 µs round trip. A 1 kHz loop uses 12% of the bus; 4 kHz is feasible. The constraint is master timing, not bandwidth.

• Hardware: a dedicated Ethernet MAC and PHY per EtherCAT segment. Do not share the port with general traffic or put a switch in the path. A switch breaks the ring and adds store-and-forward delay.
• Where the stack runs: three common options.
  • On the main SoC under a real-time Linux (PREEMPT_RT) with an isolated CPU core, using the IgH EtherCAT Master or SOEM. Lowest cost; worst-case latency must be measured.
  • On a dedicated real-time processor on the carrier (for example a TI AM243x or AM64x, or an Arm Cortex-R/M class MCU) that owns the EtherCAT port and exchanges setpoints with the SoC over shared memory or SPI/PCIe. Best determinism; isolates the control loop from the AI workload.
  • A commercial stack (Beckhoff TwinCAT, acontis EC-Master) for certified tooling and diagnostics.
• Timing: the master must send each frame early enough that it reaches every slave before SYNC0. Distributed clocks absorb send jitter, so the requirement is a bounded deadline, not microsecond-exact send times.
• Redundancy: a second master port connected to the far end of the line turns it into a ring. If a cable breaks, both ends still reach every slave. This needs PHYs with fast link-loss detection.
• Safety: safe torque off should not depend on the AI SoC. Route an FSoE master or a hardwired STO from the safety MCU.
• PHY choice: pick from the compliant list (for example TI DP83826 or Microchip KSZ8081). Disable EEE and enable fast link drop.

Say it this wayI'd give EtherCAT its own MAC and PHY, no switch, and run the master on a real-time core that's isolated from the inference workload, either an isolated core under PREEMPT_RT or a dedicated MCU. A second port on the far end gives ring redundancy, and safety stays on its own path through FSoE or hardwired STO.

• EtherCAT introduction (ETG) — your local copy. Best single overview of the protocol, topology and performance.
• EtherCAT Overview & ETG Introduction brochure. Official ETG summary.
• Beckhoff ESC datasheet, Section I: Technology. The real reference for ports, frame processing, FMMU, SyncManagers and distributed clocks.
• Beckhoff ESC datasheet, Section II: Registers. Register map for when you need specifics.
• Beckhoff ET1100 hardware datasheet. Pinout, PHY connection, clocking and PDI options for the classic ESC.
• Beckhoff application note: PHY Selection Guide v3.1. Source of the PHY requirements table on this page.
• Beckhoff application note: ESC comparison v2.8. Feature comparison across ESC parts and IP cores.
• ETG.2200 Slave Implementation Guide. How to design a slave: hardware, firmware, conformance.
• ETG application note: EtherCAT P Implementation Guide. Power and data on one cable.
• Beckhoff Infosys: EtherCAT Distributed Clocks. Detailed explanation of delay measurement and drift compensation.
• TI SPRAD72: Using SMI of C2000 EtherCAT Slave Controller for PHY Configuration. PHY latency and fast link-drop configuration example.
• TI DP83826 low-latency 10/100 PHY. A PHY on Beckhoff's compliant list.
• Microchip AN1916: Integrating LAN9252 SDK with Beckhoff's EtherCAT SSC. Getting a LAN9252 slave running with the standard stack.
• TI TIDA-010979 schematics — your local copy. A joint motor control reference design with industrial communication; useful to see a real slave board.
• SOEM (Simple Open EtherCAT Master). Open-source master library.
• IgH EtherCAT Master (EtherLab). Open-source Linux kernel master.