reference sheet · synchronous buck
Every parameter that moves efficiency, ripple, transient response, stability, EMI and thermals in a buck converter, with the equations, the trade-offs, and a worked 48 V → 12 V design. The worked numbers and the calculator use representative 100 V-class silicon values; swap in datasheet values for a real design.
A buck chops the input with a high-side switch, then an LC low-pass filter averages the switch-node square wave. In steady state the inductor's volt-seconds balance to zero each cycle, which sets the duty cycle: ideally D = Vout/Vin.
Q1 on: Vin − Vout across L, current ramps up. Q1 off, Q2 on: −Vout across L, current ramps down. The amber loop carries pulsed current with fast edges; its inductance sets ringing, overshoot and much of the EMI.
Continuous conduction mode (CCM). If Iout drops below ΔIL/2 the valley reaches zero: an asynchronous buck (or a synchronous one in diode emulation) enters DCM; a forced-PWM synchronous buck keeps going and lets current go negative.
CCM, steady state. Ts = 1/fsw. r = ΔIL/Iout is the current ripple ratio.
Efficiency η = Pout/(Pout + ΣPloss). Losses fall into three groups that scale differently with load. Knowing which group dominates at the operating point tells you which parameter to change.
| Loss | Equation | Scales with | Main levers |
|---|---|---|---|
| HS conduction | I_out²·D·(1+r²/12)·R_DS(on),HS(T_j) | I², D, Tj | Lower RDS(on) (bigger die, but more Qg), higher VGS, cooler junction |
| LS conduction | I_out²·(1−D)·(1+r²/12)·R_DS(on),LS(T_j) | I², 1−D | At low D this is the bigger conduction term; pick LS for lowest RDS(on) |
| HS V-I overlap | ½·V_in·f_sw·(I_v·t_on + I_pk·t_off) | Vin, I, fsw | Low Qgd + Qgs2, strong driver, low Rg, low common-source inductance |
| t ≈ (Q_gd + Q_gs2)/I_g ; I_g,on = (V_drv − V_pl)/(R_drv + R_g) | Turn-off current is the plateau voltage divided by pull-down resistance, so a low-Vth FET turns off slowly. | ||
| Coss charge | ≈ ½·Q_oss·V_in·f_sw (per hard-switched node) | Vin, fsw | Low Qoss; soft switching (ZVS) recovers it. Grows fast at 48 V |
| Reverse recovery | Q_rr·V_in·f_sw (+ extra HS turn-on loss) | Vin, fsw, I, di/dt | Short dead time, Schottky-integrated LS, GaN (Qrr = 0). Also a ringing source |
| Dead-time conduction | V_SD·f_sw·(I_v·t_d1 + I_pk·t_d2) | I, fsw, tdead | Adaptive or predictive dead time; GaN's 2–3 V reverse drop makes this matter more |
| Gate drive | (Q_g,HS + Q_g,LS)·V_drv·f_sw | fsw, Vdrv | Lower Qg, optimal Vdrv |
| Driver supply (LDO) | (Q_g,HS + Q_g,LS)·f_sw·(V_in − V_drv) | Vin, fsw | At 48 V the internal LDO burns ~9× the gate power. Feed VCC from Vout or an aux rail (EXTVCC pin) |
| Inductor copper DC | I_L,rms²·DCR(T) | I², temperature (+0.39%/°C Cu) | Bigger wire, fewer turns, flat wire, larger body |
| Inductor copper AC | (ΔI_L/√12)²·R_ac(f) | ripple, fsw | Skin/proximity: litz, foil, or lower ripple. Usually minor below 1 MHz |
| Inductor core | P_v = k·f^α·ΔB^β · V_e (Steinmetz; iGSE for non-sine) | ΔB (ripple), fsw | Material choice; ΔB = L·ΔIL/(N·Ae). Nearly load-independent in CCM |
| Input cap ESR | I_Cin,rms²·ESR | I², D(1−D) | Parallel MLCCs; also sets cap self-heating |
| Output cap ESR | (ΔI_L/√12)²·ESR | ripple | Usually negligible |
| PCB / sense resistor | I_out²·(R_trace + R_sense) | I² | Copper weight, planes, DCR or RDS(on) sensing instead of a shunt |
| Controller quiescent | I_q·V_in | Vin | Matters for standby and light-load η |
| Snubber | ≈ C_snub·V_in²·f_sw | Vin², fsw | Use only as much RC as the ringing needs; fix loop inductance first |
| Feedback divider | V_out² / (R_top + R_bot) | fixed | Higher R saves standby power but adds noise pickup |
Qrr and Coss at high input voltage. Both scale with Vin and fsw and not with load, so on a 48 V bus they can exceed the conduction losses. In the worked example below they are about a third of the total. That is the core argument for GaN on 48 V rails.
Gate drive taken linearly from Vin. Qg·fsw·Vin, not Qg·fsw·Vdrv. A bias rail fed from Vout recovers most of it.
Effect of increasing each parameter, all else held. ▲ better, ▼ worse, ◆ depends / trade-off, — little effect.
| Increase… | Efficiency | Out ripple | Transient | Size | EMI | Notes |
|---|---|---|---|---|---|---|
| fsw | ▼ | ▲ | ▲ | ▲ smaller L, C | ◆ | Switching, Qrr, Coss, gate, core losses scale with f. Higher f moves harmonics up but makes min on-time harder. Automotive: avoid 530 kHz–1.8 MHz AM band. |
| L | ◆ | ▲ | ▼ slew-limited | ▼ | ▲ | Lower ripple cuts RMS and core loss but raises DCR for the same size. Slower current slew means more Cout for transients. |
| Cout | — | ▲ | ▲ | ▼ | — | Lowers fLC, so crossover and compensation shift. Watch DC-bias derating on MLCCs. |
| Cin | ▲ slight | — | ▲ | ▼ | ▲ | Lowers input ripple and ESR heating; must meet RMS current. Can interact with input filter (damping). |
| Vin | ▼ | ▼ | ◆ | — | ▼ | Switching, Coss, Qrr grow; ripple grows; D shrinks toward min on-time. Faster load-application slew. |
| Vout (higher D) | ▲ usually | ◆ | ◆ | — | — | Same I, more Pout, fixed losses amortized. Ripple ∝ Vout(1−D) peaks at D = 0.5. |
| Iout | ◆ peak then ▼ | — | — | — | ▼ | See efficiency curve. Thermal limits set the ceiling. |
| Ripple ratio r | ◆ | ▼ | ▲ | ▲ smaller L | ▼ | Higher r: smaller L, faster response, more RMS, core and turn-off loss, earlier DCM. |
| RDS(on) | ▼ heavy load | — | — | ▲ smaller die | — | Lower RDS(on) brings higher Qg, Coss; optimize per FOM. |
| Qg, Qgd | ▼ light load / high f | — | — | — | ▲ slower edges | Slower edges ease EMI but cost loss. |
| Qrr | ▼ | — | — | — | ▼ | Recovery current spike drives switch-node ringing. |
| Dead time | ◆ | — | — | — | ◆ | Too short: shoot-through. Too long: diode loss and Qrr. Optimal is a few ns more than the turn-off delay. |
| Gate drive V | ◆ | — | — | — | ▼ faster edges | Lower RDS(on) vs Qg·V loss. GaN: hard 6 V limit. |
| Gate resistor Rg | ▼ | — | — | — | ▲ | Tunes dv/dt and ringing. Split turn-on/turn-off with a diode. |
| Inductor DCR | ▼ | — | — | ▲ smaller part | — | Also usable as a lossless current sense (RC matched to L/DCR). |
| Cap ESR | ▼ slight | ▼ | ▼ | — | — | But ESR zero helps phase in VMC and provides ripple for COT. |
| Loop crossover fc | — | — | ▲ | ▲ less Cout | — | Limited to ~fsw/10 (VMC) or fsw/5–/6 (PCMC). Too high: noise and jitter. |
| Hot-loop inductance | ▼ | ▼ spikes | — | — | ▼ | Overshoot V = L·di/dt eats voltage margin; ringing at 1/(2π√(Lloop·Coss)). |
| Common-source inductance | ▼ | — | — | — | ◆ | Negative feedback on VGS slows switching. Kelvin-source packages fix it. |
| Ambient / Tj | ▼ | — | — | — | — | RDS(on) and DCR rise; ferrite core loss has a minimum near 80–100 °C. |
| Phases (N) | ▲ heavy load | ▲ cancellation | ▲ | ◆ | ▲ | Effective ripple frequency N·fsw; Cin RMS falls; adds controller and current-sharing complexity. |
| Method | Plant seen by the loop | Compensator | Strengths | Weak points |
|---|---|---|---|---|
| Voltage mode (VMC) | LC double pole at fLC, Q set by load and ESR; 180° phase drop; ESR zero | Type III (two zeros near fLC, poles at fESR and fsw/2) | Fixed frequency, good noise immunity, works at very low D, easy multiphase sync | Harder to compensate; gain ∝ Vin unless feed-forward; no inherent cycle current limit |
| Peak current mode (PCMC) | Single pole fp ≈ 1/(2π·Rload·Cout), ESR zero, double pole at fsw/2 | Type II | Easy compensation, inherent cycle-by-cycle limit, line rejection, natural current sharing | Subharmonic oscillation at D > 0.5 without slope compensation; leading-edge blanking raises ton,min; noise sensitive at light load |
| Valley current mode | As PCMC, mirror image | Type II | Good for low D (senses during long off-time) | Subharmonic at D < 0.5 without slope comp; limits valley, not peak |
| Constant on-time (COT) / D-CAP | Ripple-based, no error amp in classic form | None or minimal | Very fast transient response; natural PFM at light load; no compensation network | Frequency varies (adaptive ton helps); needs ripple: ESR·Cout > ton/2 or ripple injection with MLCCs; DC offset from ripple |
| Hysteretic | Comparator with band | None | Fastest, simplest | Variable frequency, EMI spectrum spreads with load |
| Digital (PMBus) | Any of the above, sampled | PID/IIR | Telemetry, programmability, adaptive dead time, non-linear transient boost | ADC quantization (limit cycling), delay, firmware qualification |
Two limits apply. The loop limits how fast the controller reacts; the inductor limits how fast current can change even when the controller responds immediately. Whichever is slower sets the overshoot.
| Parameter | 100 V Si trench | 100 V e-mode GaN | Effect on the buck |
|---|---|---|---|
| Qrr | Tens of nC | Zero (no body diode) | Removes recovery loss and the ringing it excites; the largest single gain at 48 V |
| Qg at similar RDS(on) | Baseline | Several times lower | Gate loss and transition time fall; higher fsw becomes practical |
| Qoss | Baseline | Roughly half or less | Lower Coss loss |
| Reverse conduction in dead time | Body diode ~0.7–0.9 V | ~1.5–3 V (depends on VGS,off) | Dead-time loss per ns is 2–3× higher; keep dead time short (few ns) |
| Gate rating | ±20 V, Vth 2–4 V | Typ. −4/+6 V abs max, Vth ~1.1–1.7 V | Tight gate regulation; Miller turn-on risk; often a negative or 0 V off-state with Kelvin source |
| Avalanche | Rated | No avalanche capability | Need voltage margin; clamp overshoot by layout |
| Edge rate | 5–20 V/ns typical | 50–100+ V/ns | Layout loop inductance and CMTI become first-order concerns; EMI filter design shifts higher in frequency |
| Package | PowerPAK, LFPAK, TOLL | Chip-scale / LGA, very low inductance | Assembly and underfill, solder-joint reliability, thermal path through board |
| Dynamic RDS(on) | No | Charge trapping raises RDS(on) after high-V blocking | Check vendor data at your Vin and fsw |
Layout is a design parameter. The same schematic can differ by several points of efficiency and 20 dB of EMI depending on placement.
A regulated converter draws constant power, so it looks like a negative resistance at its input: Rin = −Vin2/Pin below the loop crossover. An undamped LC input filter can oscillate with it. Keep the filter's output impedance well below |Rin| at all frequencies, especially at the filter's resonance. Damp it with an electrolytic's ESR or an RC branch (R ≈ √(Lf/Cf), Cd ≈ 4 × Cf). At 48 V and 100 W, |Rin| ≈ 23 Ω; at 12 V input the same power gives 1.4 Ω, which is why low-voltage high-power filters are harder.
| Feature | What it does | Design parameters |
|---|---|---|
| UVLO / enable | Keeps the converter off until Vin can sustain regulation; hysteresis prevents chatter | Rising/falling thresholds via EN divider; set above dropout Vin,min |
| Soft-start | Ramps reference so inrush stays below current limit | tss; Cout including downstream load caps |
| Pre-bias start-up | Prevents the low side from discharging a rail already powered by another source | Required for sequenced or redundant rails |
| Overcurrent | Cycle-by-cycle peak or valley limit; then hiccup or latch-off | Limit above Ipk max with tolerance, below Isat; hiccup duty keeps short-circuit dissipation low |
| Short-circuit | At Vout ≈ 0, required on-time is near zero, so the min on-time lets current run away | Valley limit, frequency foldback or hiccup handle it |
| OVP / UVP | Latches or turns on LS to crowbar on output fault | Thresholds relative to Vref; coordinate with downstream absolute max |
| Thermal shutdown | Die temperature trip with hysteresis | Only protects the controller die, not external FETs; add NTC if needed |
| Power good | Open-drain flag when Vout is in window | Delay and window; drives sequencing and resets |
| Light-load mode | FCCM (fixed f, sinks current), PFM / skip / burst (high light-load η, variable spectrum), diode emulation | Choose per EMI and efficiency priorities; some parts allow ultrasonic mode to keep f > 20 kHz |
| Sync / interleave | Lock to external clock; phase shift between converters | Reduces input RMS and beat tones |
| Tracking / sequencing | Rails ramp in order or ratiometrically | FPGA/SoC rail requirements |
| Option | When it helps | Cost |
|---|---|---|
| Multiphase interleaved buck | High current (> 20–30 A), fast transients, thermal spreading. Ripple cancels fully at D = k/N | Controller, current sharing, more parts |
| Two-stage (48 → 12 → 1 V) | Large step-down; each stage runs at a sensible duty and its own optimal fsw | Efficiencies multiply (0.97 × 0.92 ≈ 0.89) |
| Fixed-ratio bus converter (DCX, switched-cap) | 48 → 12 V at 98%+ unregulated, followed by regulated POL bucks | No regulation; output tracks input |
| Three-level / flying-capacitor buck | Halves switch voltage stress, doubles effective ripple frequency, smaller inductor | Flying-cap balancing, more switches |
| Hybrid switched-cap buck | Large ratios in very small volume (data center, robotics compute) | Complex control, start-up |
| Tapped-inductor buck | Extends duty at large ratios | Leakage-inductance spikes |
| Power module / integrated stage | Schedule, layout risk, size | Price, less freedom in thermal and EMI tuning |
A plausible auxiliary rail on a robot's 48 V bus (sensors, small compute, fans). Representative 100 V silicon values, junction assumed hot (RDS(on) × 1.4). Vin range 36–58 V.
| D (nominal) | 0.25 |
| Target r | 0.35 |
| L (calc 8.04 µH) → choose | 8.2 µH |
| ΔIL at 48 V | 2.74 A |
| ΔIL at 58 V | 2.90 A |
| Ipk / Ivalley | 9.37 / 6.63 A |
| IL,rms | 8.04 A |
| Isat required (with 20% margin + CL) | ≥ 12 A |
| ICin,rms | 3.46 A |
| Cout effective (after DC bias) | 40 µF |
| Ripple, capacitive term | 21 mV p-p |
| fLC | 8.8 kHz |
| Crossover target (fsw/10) | 40 kHz |
| ton at 58 V | 517 ns ✓ |
| Unload 4 A step, L-limited overshoot | ≈ 137 mV |
| Loss | W | % |
|---|---|---|
| HS V-I overlap (5 ns edges) | 0.77 | 21.5 |
| LS Qrr (40 nC) | 0.77 | 21.5 |
| Inductor DCR (8 mΩ) | 0.52 | 14.5 |
| Coss (Qoss 40 nC) | 0.38 | 10.8 |
| LS conduction (4 mΩ) | 0.27 | 7.6 |
| Inductor core | 0.20 | 5.6 |
| PCB copper (3 mΩ) | 0.19 | 5.4 |
| HS conduction (6 mΩ) | 0.14 | 3.8 |
| Dead time (2 × 20 ns) | 0.10 | 2.9 |
| Gate drive (50 nC, 5 V) | 0.10 | 2.8 |
| Controller Iq | 0.10 | 2.7 |
| Cin ESR | 0.04 | 1.0 |
| Total | 3.57 | 100 |
| Efficiency (96 W out) | 96.4% |
ROHM's application note Efficiency of Buck Converter (64AN035E Rev.004, Nov 2022) breaks a buck's loss into twelve closed-form terms and works them for a 12 V → 5 V, 3 A, 1 MHz converter with small integrated MOSFETs. It is the low-voltage, high-frequency counterpart to the 48 V example in section 16, and the two together show how the dominant loss moves with input voltage.
| VIN / VOUT / IOUT | 12 V / 5.0 V / 3.0 A | fSW / L / DCR | 1.0 MHz / 4.7 µH / 80 mΩ |
| RON-H / RON-L | 100 / 70 mΩ | tr-H / tf-H | 4 / 6 ns |
| tr-L / tf-L | 2 / 2 ns | Dead time tDr / tDf | 30 / 30 ns |
| Body diode VD | 0.5 V | IRR / tRR | 0.3 A / 25 ns |
| CDS = CGD (each FET) | 40 pF | Qg-H = Qg-L / Vgs | 1 nC / 5.0 V |
| IC current ICC | 1.0 mA | ESRIN / ESROUT | 3 / 1 mΩ |
| Derived: D / ΔIL | 0.417 / 0.62 A | Derived: IP / IV | 3.31 / 2.69 A |
| Term | ROHM equation | Sync | Async | % of sync |
|---|---|---|---|---|
| Inductor DCR | [I_OUT² + (I_P−I_V)²/12]·DCR | 723 mW | 723 mW | 39.7 |
| HS conduction | [I_OUT² + (I_P−I_V)²/12]·R_ON-H·V_OUT/V_IN | 376 mW | 376 mW | 20.7 |
| LS conduction / diode conduction | […]·R_ON-L·(1−V_OUT/V_IN) | I_OUT·V_F·(1−V_OUT/V_IN) | 369 mW | 875 mW | 20.3 |
| HS switching | ½·V_IN·I_OUT·(t_r-H + t_f-H)·f_SW | 180 mW | 180 mW | 9.9 |
| Dead time | V_D·I_OUT·(t_Dr + t_Df)·f_SW | 90 mW | — | 4.9 |
| Reverse recovery | ½·V_IN·I_RR·t_RR·f_SW | 45 mW | 45 mW | 2.5 |
| IC operation | V_IN·I_CC | 12 mW | 12 mW | 0.7 |
| Gate charge | (Q_g-H + Q_g-L)·V_gs·f_SW or (C_GS-H + C_GS-L)·V_gs²·f_SW | 10 mW | 5 mW | 0.5 |
| Input cap ESR | [I_OUT·√((V_IN−V_OUT)·V_OUT)/V_IN]²·ESR_IN | 6.6 mW | 6.6 mW | 0.4 |
| COSS | ½·(C_DS-H + C_GD-H)·V_IN²·f_SW | 5.8 mW | 5.8 mW | 0.3 |
| LS switching | ½·V_D·I_OUT·(t_r-L + t_f-L)·f_SW | 3 mW | — | 0.2 |
| Output cap ESR | [ΔI_L/(2√3)]²·ESR_OUT | 0.03 mW* | 0.03 mW* | 0.0 |
| Total loss | 1.82 W | 2.23 W | 100 | |
| Efficiency (15 W out) | η = V_OUT·I_OUT / (V_OUT·I_OUT + P) | 89.2% | 87.1% |
Every value above was recomputed from the stated conditions and matches the note, with one exception: *the note lists 0.5 mW for the output capacitor; its own formula with these values gives 0.03 mW. Negligible either way. The note gives the loss totals but not the efficiencies; those are computed here.
| Condition | Dominant loss | Remedy |
|---|---|---|
| High IOUT | FET and inductor conduction | Lower RON and DCR, accepting larger parts and more capacitance |
| Low IOUT | Switching, COSS, gate, IC | Lower fSW, smaller FETs, low-Iq control |
| High fSW | Switching, recovery, COSS, dead time | Low-capacitance fast FETs, shorter dead time |
| Low VOUT (low D) | Low-side conduction | Lowest-RON low side; synchronous over diode |
| High VOUT (high D) | High-side conduction | Lower high-side RON; diode penalty shrinks |
| Item | ROHM note | This sheet | When it matters |
|---|---|---|---|
| Switching current | IOUT at both edges | IV at turn-on, IP at turn-off | Equal for symmetric edges; differs when tr ≠ tf or ripple is large |
| Dead time current | IOUT | IV and IP per edge | High ripple ratio, or negative valley at light load |
| Reverse recovery | Triangle ½·IRR·tRR, i.e. Qrr ≈ 3.75 nC | Qrr·Vin·fsw | Same physics; datasheets usually give Qrr directly |
| COSS | ½·C·VIN2, high side only; low side treated as zero-voltage switched | ½·Qoss·Vin per hard-switched node | Use charge or energy-equivalent Co(er): COSS is strongly non-linear with VDS |
| Inductor core and AC copper | Not covered | Steinmetz / iGSE, Rac | Ferrite at MHz, or high ripple; often 5–15% of loss |
| Gate drive supply | Qg·Vgs·f | Adds LDO loss Qg·f·(Vin − Vdrv) | High VIN with internal bias regulator |
| Temperature | RON, DCR at given values | Hot factor on RDS(on) | Always; iterate to the operating Tj |
| PCB copper | Not covered | I2·Rtrace | High current |
Forced-CCM synchronous buck, first-order models from section 03. The ROHM preset reproduces the section 17 app-note example to within 3 mW. Results are estimates; vendor models and bench data govern.
Measure, don't guess. IR image first: the hottest part points to the loss. Compare light-load η (fixed losses) with full-load η (I²R). Check switch-node ringing (Qrr, snubber), dead time on the scope, actual RDS(on) at the real VGS, driver bias supply source, inductor saturation (peaky current waveform), and whether the controller entered PFM or is skipping pulses.
Switching, Qrr, Coss, gate and core losses scale with f. Higher f shrinks L and C, raises the achievable crossover (faster transients, less Cout), and can move harmonics out of a protected band. With GaN the per-cycle loss is low enough that 1–2 MHz at 48 V becomes reasonable.
Choose ripple ratio (0.2–0.4) at Vin,max, compute L, then select a part with Isat above the peak at current limit and max temperature, Irms rating with derating, and the best DCR-plus-core-loss trade for your frequency, checked in the vendor loss tool. Prefer soft saturation if overloads are possible.
In peak current mode above 50% duty, a perturbation in inductor current grows each cycle because the down-slope is steeper than the up-slope in the error map. It appears as alternating wide and narrow pulses at fsw/2. Adding a compensating ramp (Se ≥ half the down-slope) restores stability.
DC-bias derating can remove most of the capacitance at the operating voltage, so ripple is higher and fLC higher than calculated, which shifts the compensation. Also temperature, aging, and acoustic noise (piezo effect) in PFM.
The required on-time at any useful frequency is below what a controller can do, and a single stage loses badly to switching loss. Use 48 → 12 V (DCX or buck) then multiphase POL bucks, or a hybrid switched-cap or 48 V direct-conversion stage. Compare total efficiency and transient performance, not the first stage alone.
Vin,max including transients (load dump, regen, hot-plug ringing) plus switch-node overshoot from Lloop·di/dt, with margin: 25–50% for Si, more for GaN, which has no avalanche rating.
PFM or burst mode bursts at audio frequencies; MLCCs and the inductor vibrate. Use ultrasonic mode or FCCM, soft-termination or film caps, or a different inductor construction.
Motor PWM produces large ripple and steps on the bus; regen can raise the bus above nominal. The buck needs line-transient rejection (current mode helps), VDS margin for regen, an input filter that stays stable against the negative input impedance, and a switching frequency planned against motor PWM harmonics and sensor bands.